w6692 Winbond Electronics Corp America, w6692 Datasheet - Page 79

• Manufacturer Part Number: w6692
• Description: Pci Bus Isdn S/t-controller
• Manufacturer: Winbond Electronics Corp America

Note: The connection with micro-controller is through HDLC controller. When HDLC connects with layer 1, either transparent
or extended transparent mode can be used. When HDLC connects with PCM port, only extended transparent mode can be used
and the EPCM bit must be set to enable PCM function.
SW56
Note: In 56 kbps mode, only transparent mode can be used.
FTS1-0
number of received data or the number of vacancies in XFIFO reaches the threshold value.
8.2.5 B1_ch Extended Interrupt Register B1_EXIR
Value after reset: 00H
RMR
RME
B1_RBCL registers. The number of data available in the B1_RFIFO equals frame lenth modulus threshold. The result of CRC
check is indicated by B1_STAR:CRCE bit.
RDOV
XFR
This interrupt indicates that up to a threshold length of data can be written into the B1_XFIFO.
Used in transparent mode only. The last block of a frame has been received. The frame length can be found in B1_RBCH +
0: The data rate in B1 channel is 64 kbps.
1: The data rate in B1 channel is 56 kbps. The most significant bit in each octet is fixed at "1".
These two bits determine the B1 channel receive and transmit FIFO's threshold setting. An interrupt is generated when the
At least a threshold lenth of data has been stored in the B1_RFIFO.
When the number of last block of a frame equals the threshold, only RME interrupt is generated.
Data overflow occurs in the receive FIFO. The incoming data will overwrite the data in the receive FIFO.
7
Transmit FIFO Ready
Receive Message End
Receive Message Ready
Switch 56 Traffic
Receive Data Overflow
FIFO Threshold Select
RMR
6
1
FTS1
0
0
1
1
RME
5
FTS0
0
1
0
1
1
RDOV
4
Threshold (byte)
Not allowed
Layer 1
Reserved
3
64
96
PCM, PCM
2
-79 -
XFR
1
HDLC
Read_clear
XDUN
0
W6692 PCI ISDN S/T-Controller
Publication Release Date:
Address 90H/24H
Preliminary Data Sheet
Sep 30, 1999
Revision 0.9