ADF4106 Analog Devices, ADF4106 Datasheet
ADF4106
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ADF4106 Summary of contents
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... AGND GENERAL DESCRIPTION The ADF4106 frequency synthesizer can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low-noise digital PFD (Phase Frequency Detector), a precision charge pump, a programmable reference divider, programmable A and B counters and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction with the dual modulus prescaler (P/P + 1), implement an N divider ( ...
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... ADF4106–SPECIFICATIONS Parameter RF CHARACTERISTICS 3 RF Input Frequency ( Input Sensitivity Maximum Allowable 4 Prescaler Output Frequency REFIN CHARACTERISTICS REFIN Input Frequency 5 REFIN Input Sensitivity REFIN Input Capacitance REFIN Input Current PHASE DETECTOR 6 Phase Detector Frequency CHARGE PUMP I Sink/Source CP High Value Low Value ...
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... The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value). 10 The phase noise is measured with the EVAL-ADF4106EB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer ( MHz @ 0 dBm) ...
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... ADF4106BCP –40°C to +85° Thin Shrink Small Outline Package (TSSOP Chip Scale Package + 0 Contact the factory for chip availability Note that aluminum bond wire should not be used with the ADF4106 die. Package Option RU-16 CP-20 WARNING! ESD SENSITIVE DEVICE ...
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... CP must be the same value must be the same value ADF4106 Chip Scale Package CPGND 1 PIN 1 15 MUXOUT INDICATOR 14 LE AGND 2 ADF4106 13 DATA AGND 3 12 CLK TOP VIEW and R is ...
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... ADF4106–Typical Performance Characteristics FREQ UNIT – GHz KEYWORD – R PARAM TYPE – S IMPEDANCE – 50 DATA FORMAT – MA FREQ MAGS11 ANGS11 FREQ 0.500 0.89148 – 17.2820 3.300 0.600 0.88133 – 20.6919 3.400 0.700 0.87152 – 24.5386 3.500 0.800 0.85855 – 27.3228 3 ...
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... 8/9 80 100 ADF4106 TUNING VOLTAGE – 100 1k 10k 100k PHASE DETECTOR FREQUENCY – Hz 16/17 32/33 64/65 PRESCALER VALUE ...
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... ADF4106 3 3.0 2.5 2.0 1.5 1.0 0 100 150 200 PRESCALER OUTPUT FREQUENCY CIRCUIT DESCRIPTION REFERENCE INPUT SECTION The Reference Input stage is shown in Figure 2. SW1 and SW2 are normally-closed switches. SW3 is normally-open. When Powerdown is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REF on power-down ...
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... DB0, as shown in the timing diagram of Figure 1. The truth table CPGND for these bits is shown in Table VI. Table I shows a summary of how the latches are programmed. Control Bits ADF4106 MUX CONTROL SDOUT Table I. C2, C1 Truth Table C1 Data Latch 0 R Counter 1 N Counter (A and B) ...
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... ADF4106 ANTI- TEST BACKLASH RESERVED MODE BITS WIDTH DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 LDP T2 T1 ABP2 RESERVED DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB23 DB22 ...
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... ABP1 ANTIBACKLASH PULSEWIDTH 0 2.9ns 1 1.3ns 0 6.0ns 1 2.9ns ADF4106 CONTROL DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 (0) C1 (0) .......... DIVIDE RATIO .......... .......... .......... .......... ...
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... ADF4106 RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 B13 B12 B11 B10 X = DON’T CARE B13 B12 B11 .......... .......... .......... .......... . . . .......... . . . .......... . . . .......... .......... .......... .......... .......... F4 (FUNCTION LATCH) FASTLOCK ENABLE ...
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... I (mA 5.1k 11k 1.06 0.625 0.289 2.12 1.25 0.580 3.18 1.875 0.870 4.24 2.5 1.160 5.30 3.125 1.450 6.36 3.75 1.730 7.42 4.375 2.020 8.50 5.0 2.320 ADF4106 CONTROL MUXOUT BITS CONTROL DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 C2 ( PD1 F1 PHASE DETECTOR COUNTER F2 POLARITY F1 OPERATION 0 NEGATIVE 0 NORMAL 1 POSITIVE ...
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... ADF4106 CURRENT CURRENT PRESCALER SETTING SETTING VALUE 2 1 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P2 P1 PD2 CPI5 CPI3 CPI2 CPI6 CPI4 TC4 CPI6 CPI5 CP14 ...
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... PD Polarity This bit sets the Phase Detector Polarity Bit. See Table V. CP Three-State This bit controls the CP output pin. With the bit set high, the CP output is put into three-state. With the bit set low, the CP output is enabled. ADF4106 ...
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... APPLICATION SECTION Local Oscillator for LMDS Base Station Transmitter Figure 7 shows the ADF4106 being used with a VCO to pro- duce the LO for an LMDS base station operation in the 5.4 GHz to 5.8 GHz band. The reference input signal is applied to the circuit at FREF and, in this case, is terminated in 50 Ω ...
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... The microconverter is set up for SPI Master Mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF4106 needs a 24-bit word. This is accomplished by writing three 8-bit bytes from the microconverter to the device. When the third byte has been written the LE input should be brought high to complete the transfer ...
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... ADF4106 On first applying power to the ADF4106, it needs at three writes (one each to the R counter latch, the N counter latch and the function latch) for the output to become active. I/O port lines on the ADuC812 are also used to control power-down (CE input) and to detect lock (MUXOUT config- ured as lock detect and polled by the port input) ...
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... SEATING 0.020 (0.50) 0.008 (0.20) PLANE BSC REF CONTROLLING DIMENSIONS ARE IN MILLIMETERS 0.256 (6.50) 0.246 (6.25 0.028 (0.70) 0.020 (0.50) 0.024 (0.60) 0.017 (0.42) 0.010 (0.25) 0.009 (0.24) MIN 0.024 (0.60) 0.017 (0.42 0.009 (0.24 0.012 (0.30) 0.080 (2.25) BOTTOM 0.009 (0.23) 0.083 (2.10) SQ VIEW 0.007 (0.18) 0.077 (1.95 0.030 (0.75 0.022 (0.60) 0.014 (0.50) 0.080 (2.00) REF ADF4106 ...
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