ADF4106 Analog Devices, ADF4106 Datasheet - Page 18

• Manufacturer Part Number: ADF4106
• Description: PLL Frequency Synthesizer
• Manufacturer: Analog Devices

ADF4106
On first applying power to the ADF4106, it needs at three writes
(one each to the R counter latch, the N counter latch and the
function latch) for the output to become active.
I/O port lines on the ADuC812 are also used to control
power-down (CE input) and to detect lock (MUXOUT config-
ured as lock detect and polled by the port input).
When operating in the mode described, the maximum SCLOCK
rate of the ADuC812 is 4 MHz. This means that the maximum
rate at which the output frequency can be changed will be 166 kHz.
ADuC812
I/O PORTS
SCLOCK
MOSI
SCLK
SDATA
CE
LE
MUXOUT
(LOCK DETECT)
ADF4106
ADSP-2181 Interface
Figure 9 shows the interface between the ADF4106 and the
ADSP-21xx Digital Signal Processor. The ADF4106 needs a
24-bit serial word for each latch write. The easiest way to
accomplish this using the ADSP-21xx family is to use the
Autobuffered Transmit Mode of operation with Alternate Framing.
This provides a means for transmitting an entire block of serial
data before an interrupt is generated. Set up the word length for
8 bits and use three memory locations for each 24-bit word. To
program each 24-bit latch, store the three 8-bit bytes, enable the
Autobuffered mode and then write to the transmit register of the
DSP. This last operation initiates the autobuffer transfer.
ADSP-21xx
I/O FLAGS
SCLOCK
MOSI
TFS
SCLK
SDATA
CE
MUXOUT
(LOCK DETECT)
LE
ADF4106