ADF4106 Analog Devices, ADF4106 Datasheet - Page 17

• Manufacturer Part Number: ADF4106
• Description: PLL Frequency Synthesizer
• Manufacturer: Analog Devices

INTERFACING
The ADF4106 has a simple SPI-compatible serial interface for
writing to the device. SCLK, SDATA and LE control the data
transfer. When LE (Latch Enable) goes high, the 24 bits which
have been clocked into the input register on each rising edge of
SCLK will get transferred to the appropriate latch. See Figure 1
for the Timing Diagram and Table I for the Latch Truth Table.
The maximum allowable serial clock rate is 20 MHz. This means
that the maximum update rate possible for the device is 833 kHz
or one update every 1.2 µs. This is certainly more than adequate
for systems which will have typical lock times in hundreds of
microseconds.
FREF
IN
1000pF
51
5.1k
1000pF
CE
CLK
DATA
LE
AV
REFIN
R
V
SET
DD
DD
ADF4106
DV
MUXOUT
DD
RF
RF
IN
IN
CP
V P
V
A
B
P
100pF
100pF
100pF
LOCK
DETECT
NOTE
DECOUPLING CAPACITORS (0.1 F/10pF) ON AV
V
BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
P
OF THE ADF4106 AND ON V
4.3k
ADuC812 Interface
Figure 8 shows the interface between the ADF4106 and the
ADuC812 microconverter. Since the ADuC812 is based on an
8051 core, this interface can be used with any 8051-based
microcontroller. The microconverter is set up for SPI Master
Mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4106 needs a
24-bit word. This is accomplished by writing three 8-bit bytes
from the microconverter to the device. When the third byte has
been written the LE input should be brought high to complete
the transfer.
1.5nF
6.2k
20pF
V
CC
CC
V940ME03
OF THE V940ME03 HAVE
1, 3, 4, 5, 7, 8,
9, 11, 12, 13
DD
, DV
100pF
DD
,
100pF
18
ADF4106
18
18
RF
OUT