bt848kpf ETC-unknow, bt848kpf Datasheet - Page 20

• Manufacturer Part Number: bt848kpf
• Description: Single-chip Video Capture For Pci
• Manufacturer: ETC-unknow

F
Pin Descriptions
Table 2. Pin Descriptions Grouped by Pin Function (4 of 6)
10
UNCTIONAL
Pin #
133
137
150
151
157
158
78
79
102
103
105
106
D
ESCRIPTION
Pin Name
REFOUT
REFOUT
YREF+
YREF–
CREF+
CREF–
CLEVEL
CLEVEL
SCL
SDA
XT0I
XT0O
XT0I
XT0O
XT1I
XT1O
I/O
O
O
I
I
I
I
I
I
I/O
I/O
A
A
A
A
A
A
Signal
Serial Clock
Serial Data
Video Timing Clock Interface (5 pins)
I
2
C Interface (2 pins)
L848A_A
Description
Output of the AGC which drives the YREF+ and CREF+ pins.
In the Bt848Aand Bt849A, the external 30 K, 30 K, and 2 K
resistors are not required. However, the 0.1 F capacitor
ground to GND is still needed (see Figure 25).
The top of the reference ladder of the Y-ADC. This should be
connected to REFOUT.
The bottom of the reference ladder of the Y-ADC. This should
be connected to analog ground (AGND).
The top of the reference ladder of the C-ADC. This should be
connected to REFOUT.
The bottom of the reference ladder of the C-ADC. This should
be connected to analog ground (AGND).
An input to provide the DC level reference for the C-ADC.
This voltage should be one half of CREF+.
In the Bt848A and Bt849A, this input is internally generated.
No external components are required.
Bus clock, output open drain.
Bit Data or Acknowledge, output open drain.
Clock Zero pins. A 28.636363 MHz (8*Fsc) fundamental (or
third harmonic) crystal can be tied directly to these pins, or a
single-ended oscillator can be connected to XT0I. CMOS
level inputs must be used. This clock source is selected for
NTSC input sources. When the chip is configured to decode
PAL but not NTSC (and therefore only one clock source is
needed), the 35.468950 MHz source is connected to this port
(XT0).
In the Bt848A and Bt849A, this is the only clock source
required to decode all video formats. If only one source is
used the frequency must be 28.636363 MHz (50 ppm) and a
series resistor must be added to the layout. Alternatively, the
Bt848A and Bt849A may be configured exactly as the Bt848
(using 28.636363 and 35.468950 MHz sources).
Clock One pins. A 35.468950 MHz (8*Fsc) fundamental (or
third harmonic) crystal can be tied directly to these pins, or a
single-ended oscillator can be connected to XT1I. CMOS
level inputs must be used. This clock source is selected for
PAL input sources. If either NTSC or PAL is being decoded,
and therefore only XT0I and XT0O are connected to a crystal,
XT1I should be tied either high or low, and XT1O must be left
floating.
Single-Chip Video Capture for PCI
Bt848/848A/849A
Brooktree
®