bt848kpf ETC-unknow, bt848kpf Datasheet - Page 53

• Manufacturer Part Number: bt848kpf
• Description: Single-chip Video Capture For Pci
• Manufacturer: ETC-unknow

Bt848/848A/849A
Single-Chip Video Capture for PCI
Brooktree
Logical Organization
®
Video and Control Data FIFO
The FIFO block accepts data from the video data format conversion process, buff-
ers the data in FIFO memory, then outputs DWORDs to the DMA Controller to be
burst onto the PCI bus.
The 630-byte data FIFO is logically organized into 3 segments: FIFO1 = 70 words
deep by 36 bits wide, FIFO2 = 35 x 36 bits, and FIFO3 = 35 x 36 bits. Each of the
140 FIFO data words provide for one DWORD of pixel data and four bits of video
control code status. This is illustrated in Figure 22. The FIFOs are large enough to
support efficient size burst transfers (16 to 32 data phases) in planar as well as
packed mode.
Figure 22. Data FIFO Block Diagram
FIFO Enable Signal
FIFO Write Signals
FIFO Write Clock
(Synchronous to
Video Decoder
(From Control
(From VDFC)
Pixel Clock)
Register)
L848A_A
Control Status Code
3
From FIFO Input Data Formatter
FIFO1
Output
Y
Cb
Cr
FI[35:32]
FIFO1
FIFO2
FIFO3
FIFO2
Output
70x36
35x36
35x36
FI[31:0]
FIFO3
Output
Pixel Data
Video and Control Data FIFO
3
F
UNCTIONAL
FIFO Read Signals
(From DMA Controller)
FIFO Read Clock
(Synchronous to
PCI Clock)
D
ESCRIPTION
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