bt848kpf ETC-unknow, bt848kpf Datasheet - Page 97

• Manufacturer Part Number: bt848kpf
• Description: Single-chip Video Capture For Pci
• Manufacturer: ETC-unknow

Bt848/848A/849A
Single-Chip Video Capture for PCI
Command and Status Register
PCI Configuration Header Location 0x04
The Command[15:0] register provides control over ability to generate and respond to PCI cycles. When a zero is writ-
ten to this register, Bt848 is logically disconnected from the PCI bus except for configuration cycles. The unused bits
in this register are set to a logical zero. The Status[31:16] register is used to record status information regarding PCI
bus related events.
Bits
[26:25]
[31]
[30]
[29]
[28]
[27]
[24]
[23]
[8]
[6]
[2]
[1]
Type
RW
RW
RW
RW
RR
RR
RR
RR
RR
RO
RR
RO
Default
0
0
0
0
0
01
0
1
0
0
0
0
Name
Detected Parity
Error
Signaled
System Error
Received
Master Abort
Received
Target Abort
Signaled Target
Abort
Address Decode
Time
Data Parity
Reported
FB2B Capable
SERR enable
Parity Error
Response
Bus Master
Memory Space
L848A_A
Description
Set when a parity error is detected, in the address or data, regard-
less of the Parity Error Response control bit.
Set when SERR is asserted.
Set when master transaction is terminated with Master Abort.
Set when master transaction is terminated with Target Abort.
Set when target terminates transaction with Target Abort. This
occurs when detecting an address parity error.
Responds with medium DEVSEL timing.
A value of 1 indicates that the bus master asserted PERR during
a read transaction or observed PERR asserted by target when
writing data to target. The Parity Error Response bit in the com-
mand register must have been enabled.
Target capable of fast back-to-back transactions.
A value of 1 enables the SERR driver.
A value of 1 enables parity error reporting.
A value of 1 enables Bt848 to act as a bus initiator.
A value of 1 enables response to Memory space accesses (target
decode to memory mapped registers).
C
ONTROL
Command and Status Register
R
EGISTER
D
EFINITIONS
87