ADSP-BF538 AD [Analog Devices], ADSP-BF538 Datasheet - Page 13

• Manufacturer Part Number: ADSP-BF538
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
Active Operating Mode—Moderate Power Savings
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. In this
mode, the CLKIN to CCLK multiplier ratio can be changed,
although the changes are not realized until the full-on mode is
entered. DMA access is available to appropriately configured L1
memories.
In the active mode, it is possible to disable the PLL through the
PLL Control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the Full-On or Sleep modes.
Table 5. Power Settings
Sleep Operating Mode—High Dynamic Power Savings
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typi-
cally an external event or RTC activity will wake up the
processor. When in the Sleep mode, assertion of wakeup causes
the processor to sense the value of the BYPASS bit in the PLL
control register (PLL_CTL). If BYPASS is disabled, the proces-
sor transitions to the full on mode. If BYPASS is enabled, the
processor will transition to the Active mode. When in the sleep
mode, system DMA access to L1 memory is not supported.
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by dis-
abling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals
such as the RTC may still be running, but will not be able to
access internal resources or external memory. This powered
down mode can only be exited by assertion of the reset interrupt
(RESET) or by an asynchronous interrupt generated by the
RTC. When in deep sleep mode, an RTC asynchronous inter-
rupt causes the processor to transition to the active mode.
Assertion of RESET while in deep sleep mode causes the proces-
sor to transition to the Full On mode.
Hibernate Operating Mode—Maximum Static Power
Savings
The hibernate mode maximizes static power savings by dis-
abling the voltage and clocks to the processor core (CCLK) and
to all the synchronous peripherals (SCLK). The internal voltage
regulator for the processor can be shut off by writing b#00 to the
Mode
Full On
Active
Sleep
Deep Sleep Disabled
Hibernate
PLL
Enabled
Enabled/
Disabled
Enabled
Disabled
PLL
Bypassed
No
Yes
Core
Clock
(CCLK)
Enabled
Enabled
Disabled Enabled
Disabled Disabled On
Disabled Disabled Off
Rev. PrD | Page 13 of 56 | May 2006
System
Clock
(SCLK)
Enabled
Enabled
Core
Power
On
On
On
FREQ bits of the VR_CTL register. This disables both CCLK
and SCLK. Furthermore, it sets the internal power supply volt-
age (V
Any critical information stored internally (memory contents,
register contents, etc.) must be written to a non-volatile storage
device prior to removing power if the processor state is to be
preserved. Since V
external pins three-state, unless otherwise specified. This allows
other devices that may be connected to the processor to have
power still applied without drawing unwanted current. The
internal supply regulator can be woken up either by a real time
clock wakeup, by CAN bus traffic, by asserting the RESET pin
or by an external source.
Power Savings
As shown in
sors support three different power domains. The use of multiple
power domains maximizes flexibility, while maintaining com-
pliance with industry standards and conventions. By isolating
the internal logic of the processor into its own power domain,
separate from the RTC and other I/O, the processor can take
advantage of Dynamic Power Management, without affecting
the RTC or other I/O devices. There are no sequencing require-
ments for the various power domains.
Table 6. Power Domains
The power dissipated by a processors are largely a function of
the clock frequency of the processors and the square of the oper-
ating voltage. For example, reducing the clock frequency by 25%
results in a 25% reduction in power dissipation, while reducing
the voltage by 25% reduces power dissipation by more than
40%. Further, these power savings are additive, in that if the
clock frequency and supply voltage are both reduced, the power
savings can be dramatic.
The dynamic power management feature of the processor
allows both the processor’s input voltage (V
quency (f
The savings in power dissipation can be modeled using the
power savings factor and % power savings calculations.
The power savings factor is calculated as:
where the variables in the equations are:
Power Domain
RTC crystal I/O and logic
All internal logic except RTC
All I/O except RTC
• f
• f
• V
CCLKNOM
CCLKRED
DDINT
DDINTNOM
Power Savings Factor
=
CCLK
) to 0 V to provide the lowest static power dissipation.
is the reduced core clock frequency
is the nominal core clock frequency
------------------------- -
f
f
) to be dynamically controlled.
CCLKNOM
CCLKRED
Table
is the nominal internal supply voltage
ADSP-BF538/ADSP-BF538F
DDEXT
6, the ADSP-BF538/ADSP-BF538F proces-
is still supplied in this mode, all of the
×
⎛
⎝
------------------------------- -
V
V
DDINTNOM
DDINTRED
⎞
⎠
2
×
DDINT
⎛
⎝
-------------- -
T
T
VDD Range
VDDRTC
VDDINT
VDDEXT
) and clock fre-
NOM
RED
⎞
⎠