ADSP-BF538 AD [Analog Devices], ADSP-BF538 Datasheet - Page 30

• Manufacturer Part Number: ADSP-BF538
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-BF538/ADSP-BF538F
External Port Bus Request and Grant Cycle Timing
Table 21
on Page 31
operations for synchronous and for asynchronous BR.
Table 21. External Port Bus Request and Grant Cycle Timing with Synchronous BR
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
BS
BH
SD
SE
DBG
EBG
DBH
EBH
and
describe external port bus request and grant cycle
Table 22 on Page 31
ARE
BR
CLKOUT
AMSx
BGH
ABE1-0
AWE
BG
ADDR19-1
BR Setup to Falling Edge of CLKOUT
Falling Edge of CLKOUT to BR Deasserted Hold Time
CLKOUT Low to xMS, Address, and RD/WR disable
CLKOUT Low to xMS, Address, and RD/WR enable
CLKOUT High to BG High Setup
CLKOUT High to BG Deasserted Hold Time
CLKOUT High to BGH High Setup
CLKOUT High to BGH Deasserted Hold Time
and
Figure 16. External Port Bus Request and Grant Cycle Timing with Synchronous BR
Figure 16
t
BS
and
Rev. PrD | Page 30 of 56 | May 2006
Figure 17
t
BH
t
t
t
SD
SD
SD
t
t
Preliminary Technical Data
DBG
DBH
TBD
Min
TBD
t
t
EBG
EBH
Max
4.5
4.5
3.6
3.6
3.6
3.6
t
t
t
SE
SE
SE
Unit
ns
ns
ns
ns
ns
ns
ns
ns