ADSP-BF538 AD [Analog Devices], ADSP-BF538 Datasheet - Page 25

• Manufacturer Part Number: ADSP-BF538
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
Asynchronous Memory Read Cycle Timing
Table 16
on Page 26
tions for synchronous and for asynchronous ARDY.
Table 16. Asynchronous Memory Read Cycle Timing with Synchronous ARDY
1
Parameter
Timing Requirements
t
t
t
t
t
t
Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
SDAT
HDAT
SARDY
HARDY
DO
HO
CLKOUT
AMSx
ABE1–0
ADDR19–1
ARE
ARDY
AOE
DATA15–0
and
describe asynchronous memory read cycle opera-
Table 17 on Page 26
DATA15–0 Setup Before CLKOUT
DATA15–0 Hold After CLKOUT
ARDY Setup Before the Falling Edge of CLKOUT
ARDY Hold After the Falling Edge of CLKOUT
Output Delay After CLKOUT
Output Hold After CLKOUT
2 CYCLES
SETUP
t
DO
and
Figure 11. Asynchronous Memory Read Cycle Timing with Synchronous ARDY
Figure 11
1
1
and
PROGRAMMED READ ACCESS
t
DO
Rev. PrD | Page 25 of 56 | May 2006
Figure 12
4 CYCLES
t
SARDY
BE, ADDRESS
t
HARDY
ACCESS EXTENDED
3 CYCLES
ADSP-BF538/ADSP-BF538F
t
SARDY
Min
2.1
0.8
TBD
TBD
0.8
t
t
HO
SDAT
READ
t
HARDY
1 CYCLE
HOLD
Max
6.0
t
HDAT
t
HO
Unit
ns
ns
ns
ns
ns
ns