ADSP-BF538 AD [Analog Devices], ADSP-BF538 Datasheet - Page 36

• Manufacturer Part Number: ADSP-BF538
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-BF538/ADSP-BF538F
Table 27. External Late Frame Sync
1
2
Parameter
Switching Characteristics
t
t
MCE = 1, TFS enable and TFS valid follow t
If external RFS/TFS setup to RSCLK/TSCLK > t
DDTLFSE
DTENLFS
TSCLK
RSCLK
TFS ("LATE", EXT.)
TFS ("LATE", INT.)
TSCLK (EXT)
TSCLK (INT)
DATA RECEIVE- INTERNAL CLOCK
DATA TRANSMIT- INTERNAL CLOCK
RFS
DR
DT
DT
DT
TFS
t
HOFSE
t
HOFSI
t
HDTI
DRIVE
DRIVE
EDGE
EDGE
Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 0
Data Enable from late FS or MCE = 1, MFD = 0
t
DFSE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
t
t
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DFSI
DDTI
DRIVE
EDGE
DRIVE
EDGE
t
t
SCLKIW
SCLKIW
DTENLFS
t
t
SFSI
t
SDRI
SFSI
t
DTENI
SCLKE
t
DTENE
and t
/2, then t
SAMPLE
SAMPLE
EDGE
EDGE
DDTLFSE
DDTE/I
.
Rev. PrD | Page 36 of 56 | May 2006
and t
t
t
HDRI
t
HFSI
HFSI
DTENE/I
Figure 22. Serial Ports
1, 2
apply; otherwise t
TSCLK / RSCLK
TSCLK / RSCLK
RSCLK
TSCLK
RFS
TFS
DATA RECEIVE- EXTERNAL CLOCK
DDTLFSE
DR
DT
DATA TRANSMIT- EXTERNAL CLOCK
t
t
HOFSE
HOFSE
t
HDTE
and t
DRIVE
DRIVE
EDGE
EDGE
DTENLFS
DRIVE
DRIVE
EDGE
EDGE
1, 2
t
t
DFSE
DFSE
t
apply.
DDTE
Preliminary Technical Data
t
t
SCLKEW
SCLKEW
Min
0
t
DDTTI
t
t
t
SFSE
SDRE
SFSE
t
DDTTE
SAMPLE
SAMPLE
EDGE
EDGE
Max
10.0
t
t
t
HDRE
HFSE
HFSE
Unit
ns
ns