MM908E622ACDWBR2 FREESCALE [Freescale Semiconductor, Inc], MM908E622ACDWBR2 Datasheet - Page 30

• Manufacturer Part Number: MM908E622ACDWBR2
• Description: Integrated Quad Half-bridge, Triple High Side and EC Glass Driver with Embedded MCU and LIN for High End Mirror
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

RESET SOURCE
High Temperature Reset
the chip temperature exceeds a certain temperature, a reset
(HTR) is generated. The reset is flagged by the HTR bit in the
Interrupt Flag Register. A HTR event will reset all registers in
the SPI excluding the RSR.
Mask register.
destruction of the part, in cases of high temperature. This bit
was foreseen for test purposes only!
Watchdog Reset
watchdog timeout or wrong watchdog timer reset. Reset is
flagged by the WDR bit in the Reset Status Register. A
Watchdog reset event will reset all registers in the SPI
excluding the RSR.
Main VREG Low Voltage Reset
falls below a certain threshold, it will pull down the RST_A
pin. Reset is flagged by the LVR bit in the Reset Status
Register. An LVR event will reset all register in the SPI,
excluding the RSR.
30
908E622
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
RST_A
The device is protected against high temperature. When
The HTR can be disabled by the HTRD bit in the Interrupt
Note: Disabling the high temperature reset can lead to
The Watchdog module generates a reset, because of a
The LVR is related to the Main VDD. When the voltage
VDD
after reset event is
MONO FLOP
Pulse Duration
removed
Figure 15. Internal Reset Routing
Reset SPI Register
Clear RSR and set
(not RSR)
POR Bit
Power On Reset
device detects a power on, the POR bit in the Reset Status
Register (RSR) is set. A power on reset will reset all registers
in the SPI including the RSR and set the POR bit.
for t
LVR Threshold). Also see
Reset pin / external Reset
RST_A pin. The reset event is flagged by the PINR bit in the
reset status register.
Reset Status Register
last reset. A power on reset sets the POR bit and clears all
other bits in the Reset Status Register. All bits can be cleared
by writing a one to the corresponding bit. Uncleared bits
remain set as long as they are not cleared by a power on
reset or by software.
indicate the source of a wake-up from Sleep mode: Either by
LIN bus activity or an event on the L0 wake-up input pin.
The POR is related to the internal 5V supply. When the
The Power On Reset circuitry will force the RST_A pin low
An external reset can be applied by pulling down the
This register contains five flags that show the source of the
In addition the register includes two flags which will
RST
after the V
SPI REGISTERS
RSR
DD
WDRE
HTRD
has reached its nominal value (above
Analog Integrated Circuit Device Data
Figure
HTR Reset Sensor
WD Reset Sensor
10, page 19).
Freescale Semiconductor
POR internal VREG
LVR Main VREG