MM908E622ACDWBR2 FREESCALE [Freescale Semiconductor, Inc], MM908E622ACDWBR2 Datasheet - Page 51

• Manufacturer Part Number: MM908E622ACDWBR2
• Description: Integrated Quad Half-bridge, Triple High Side and EC Glass Driver with Embedded MCU and LIN for High End Mirror
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Analog Die System Trim Values
outlined datasheet values, the analog die needs to be
trimmed. For this purpose, 3 trim values are stored in the
Flash memory at addresses $FDC4 - $FDC6. These values
have to be copied into the analog die SPI registers:
SPI register after a reset, to ensure proper trimming of the
device.
System Test Register (SYSTEST)
testing and is not allowed to be written into.
Analog Integrated Circuit Device Data
Freescale Semiconductor
Reset
Read
Write
For improved application performance, and to ensure the
• copy $FDC4 into SYSTRIM1 register $0F
• copy $FDC5 into SYSTRIM2 register $10
• copy $FDC6 into SYSTRIM3 register $11
Note: These values have to be copied to the respective
The System Test Register is reserved for production
Note: do not write to the reserved bits
Table 14. Window Clear Interval
reser
Window
Register Name and Address: SYSTEST - $0E
Bit7
ved
Range
0
1
2
reser
ved
6
0
Select bits
Period
reser
00
01
10
11
00
01
10
11
ved
5
0
reser
ved
4
0
11.5
6.5
92
46
23
52
26
13
reser
Watchdog Period
ved
3
0
15.5
t_wd
124
8.5
62
31
68
34
17
reser
ved
2
0
reser
ved
1
0
ms
ms
reser
Bit0
ved
0
15.5
7.75
4.25
8.5
Effective Open Window
62
31
34
17
System Trim Register 1 (SYSTRIM1)
HVDDT1:0 - HVDD Over-current Shutdown Delay Bits
Table 15. HVDD Over-current Shutdown Selection Bits
ITRIM3:0 - IRef Trim Bits
Reset
Read
Write
These read/write bits allow changing the filter time (for
capacitive load) for the HVDD over-current detection.
Reset clears the HVDDT1:0 bits an sets the delay to the
maximum value.
These write only bits are for trimming the internal current
references IRef (also A0, A0CST). The provided trim
values have to be copied into these bits after every reset.
Reset clears the ITRIM3:0 bits.
Note: do not change (set) the reserved bits
11.5
6.5
92
46
23
52
26
13
HVDDT1
HVD
DT1
Bit7
0
Register Name and Address: IBIAS - $0F
0
0
1
1
HVD
DT0
ms
ms
6
0
reser
ved
5
0
0
LOGIC COMMANDS AND REGISTERS
19.25
9.625
10.75
5.375
38.5
21.5
HVDDT0
FUNCTIONAL DEVICE OPERATION
77
43
Optimal Clear Interval
reser
ved
0
1
0
1
4
0
0
ITRI
M3
ms
ms
3
0
ITRI
M2
typical Delay
2
0
±19.5%
±20.9%
950 μ s
536 μ s
234 μ s
78 μ s
ITRI
M1
1
0
908E622
ITRI
Bit0
M0
0
51