MM908E622ACDWBR2 FREESCALE [Freescale Semiconductor, Inc], MM908E622ACDWBR2 Datasheet - Page 47

• Manufacturer Part Number: MM908E622ACDWBR2
• Description: Integrated Quad Half-bridge, Triple High Side and EC Glass Driver with Embedded MCU and LIN for High End Mirror
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

MCU. The on-chip regulator consist of two elements, the
main regulator, and the low voltage reset circuit.
and provides a regulated V
the device. The output of the regulator is also connected to
the VDD pin to provide the 5.0V to the microcontroller.
Run Mode
provide a regulated supply to all digital sections.
908E622 SERIAL PHERIPHERAL INTERFACE (SPI)
communication link between the MCU and the analog die.
• MOSI - Master Out Slave In (internal pulldown)
• MISO - Master In Slave Out
• SPSCK - Serial Clock (internal pulldown)
• SS - Slave Select (internal pullup)
• During the inactive phase of SS, the new data transfer will
• The MOSI and MISO will change data on a rising edge of
• The MOSI and MISO will be sampled on a falling edge of
• The data transfer is only valid, if exactly 16 sample clock
SPSCK
Analog Integrated Circuit Device Data
Freescale Semiconductor
MOSI
MISO
The V
During RUN mode, the main voltage regulator is on. It will
The Serial Peripheral Interface (SPI) creates the
The interface consists of four pins
be prepared. The falling edge on the SS line, indicates the
start of a new data transfer (framing) and puts MISO in the
low impedance mode. The first valid data is moved to
MISO with the rising edge of SPSCK.
SPSCK.
SPSCK.
edges are present in the active phase of SS.
SS
DD
Rising edge of SPSCK
Change MISO/MOSI
regulator accepts an unregulated input supply
Output
R/W
S7
DD
Falling edge of SPSCK
Sample MISO/MOSI
Input
supply to all digital sections of
A4
S6
Read/Write, Address, Parity
A3
S5
System Status Register
A2
S4
LOGIC COMMANDS AND REGISTERS
A1
S3
A0
S2
Figure 31. SPI Protocol
Slave latch
register address
S1
P
S0
X
STOP Mode
of suppling a regulated output voltage. The Stop mode
regulator has a limited output current capability.
SLEEP Mode
turned off and the LVR circuitry will force the RST_A pin low.
The master sends address and data, the slave returns
system status and the data of the selected address.
• After a write operation the transmitted data will be latched
• Register read data is internally latched into the SPI, at the
• SS high will force MISO to a high impedance
Master Address Byte
A4 - A0
During STOP mode, the Stop mode regulator will take care
In Sleep mode, the main voltage regulator external V
A complete data transfer via the SPI, consists of 2 bytes.
into the register, by the rising edge of SS.
time when the parity bit is transferred
includes the address of the desired register.
D7
D7
D6
D6
D5
D5
LOGIC COMMANDS AND REGISTERS
Data (Register write)
Data (Register read)
FUNCTIONAL DEVICE OPERATION
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Slave latch
data
908E622
DD
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is