DP83950BNU NSC [National Semiconductor], DP83950BNU Datasheet - Page 36

• Manufacturer Part Number: DP83950BNU
• Manufacturer: NSC [National Semiconductor]

Figure 5 9 shows the RIC connected to the Inter-RIC bus via
5 0 Functional Description
5 4 DESCRIPTION OF
HARDWARE CONNECTION FOR
INTER-RIC BUS
When considering the hardware interface the Inter-RIC bus
may be viewed as consisting of three groups of signals
1 Port Arbitration chain namely ACKI and ACKO
2 Simultaneous drive and sense signals i e ACTN and
3 Drive or sense signals i e IRE IRD IRC and COLN
The first set of signals are either used as point to point links
or with external arbitration logic In both cases the load on
these signals will not be large so that the on-chip drivers are
adequate This may not be true for signal classes (2) and
(3)
The Inter-RIC bus has been designed to connect RICs to-
gether directly or via external bus transceivers The latter is
advantageous in large repeaters In the second application
the backplane is often heavily loaded and is beyond the
drive capability of the on-chip bus drivers The need for
simultaneous sense and drive capabilities on the ACTN and
ANYXN signals and the desire to allow operation with exter-
nal bus transceivers makes it necessary for these bus sig-
nals to each have a pair of pins on the RIC One driving the
bus the other sensing the bus signal When external bus
transceivers are used they must be open collector open
drain to allow wire-ORing of the signals Additionally the
drive and sense enables of the bus transceiver should be
tied in the active state
When the RIC is used in a stand alone configuration it is
required to tie ACTN
The uni-directional nature of information transfer on the IRE
IRD IRC and COLN signals means a RIC is either driving
these signals or receivng them from the bus but not both at
the same time Thus a single bi-directional input output pin
is adequate for each of these signals In an external bus
transceiver is used with these signals the Packet Enable
‘‘PKEN’’ RIC output pin performs the function of a drive
enable and sense disable
external bus transceivers such as National’s DS3893A bus
transceivers
Some bus transceivers are of the inverting type To allow
the Inter-RIC bus to utilize these transceivers the RIC may
ANYXN (Potentially these signals may be driven by multi-
ple devices)
(Only one device asserts these signals at any instance in
time )
D
to ACTN
S
and ANYXN
(Continued)
D
to ANYXN
S
36
be configured to invert the active states of the ACTN
ANYXN COLN and IRE signals Instead of being active low
they are active high
Thus they become active low once more when passed
through an inverting bus driver This is particularly important
for the ACTN and ANYXN bus lines since these signals
must be used in a wired-or configuration Incorrect signal
polarity would make the bus unusable
5 5 PROCESSOR AND DISPLAY INTERFACE
The processor interface pins which include the data bus
address bus and control signals actually perform three op-
erations which are multiplexed on these pins These opera-
tions are
1 The Mode Load Operation which performs a power up
2 Display Update Cycles which are refresh operations for
3 Processor Access Cycles which allows P’s to commu-
These three operations are described below
Mode Load Operation
The Mode Load Operation is a hardware initialization proce-
dure performed at power on It loads vital device configura-
tion information into on-chip configuration registers In addi-
tion to its configuration function the MLOAD pin is the RIC’s
reset input When MLOAD is low all of the RIC’s repeater
timers state machines segment partition logic and hub
management logic are reset
The Mode Load Operation may be accomplished by attach-
ing the appropriate set of pull up and pull down resistors to
the data and register address pins to assert logic high or low
signals onto these pins and the providing a rising edge on
the MLOAD pin as is shown in Figure 5 10 The mapping of
chip functions to the configuration inputs is shown in Table
5 1 Such an arrangement may be performed using a simple
resistor capacitor diode network Performing the Mode
Load Operation in this way enables the configuration of a
RIC that is in a simple repeater system (one without a proc-
essor)
Alternatively in a complex repeater system the Mode Load
Operation may be performed using a processor write cycle
This would require the MLOAD pin be connected to the
CPU’s write strobe via some decoding logic and included in
the processor’s memory map
initialization cycle upon the RIC
updating the display LEDs
nicate with the RIC’s registers