DP83950BNU NSC [National Semiconductor], DP83950BNU Datasheet - Page 60

• Manufacturer Part Number: DP83950BNU
• Manufacturer: NSC [National Semiconductor]

D(3 0)
D(7 4)
8 0 RIC Registers
Real Time Interrupt Register (Address 0FH)
The Real Time Interrupt register (RTI) contains information which may change on a packet by packet basis Any remaining
interrupts which have not been serviced before the following packet is transmitted are cleared Since multiple interrupt sources
may be displayed by the RTI a priority scheme is implemented A read cycle to the RTI gives the interrupt source and an address
vector indicating the RIC port which generated the interrupt The order of priority for the display of interrupt information is as
follows
1 The receive source of network activity (Port N)
2 The first RIC port showing collision
3 A port partitioned or reconnected
During the repetition of a single packet it is possible that multiple ports may be partitioned or alternatively reconnected The
ports have equal priority in displaying partition reconnection information This data is derived from the ports by the RTI register
as it polls consecutively around the ports
Reading the RTI clears the particular interrupt If no interrupt sources are active the RTI returns a no valid interrupt status
The following table shows the mapping of interrupt sources onto the D3 to D0 pins Essentially each of the three interrupt
sources has a dedicated bit in this field If a read to the RTI produces a low logic level on one of these bits then the interrupt
source may be directly decoded Associated with the source of the interrupt is the port where the event is occurring If no
unmasked events (receive collision etc ) have occurred when the RTI is read then an all ones pattern is driven by the RIC onto
the data pins
Bit
PA3
PA3
PA3
IVCTR3
D7
1
D7
R W
R
R
IVCTR2
PA2
PA2
PA2
D6
D6
1
IVCTR(3 0)
ISCR(3 0)
Symbol
Access
IVCTR1
PA1
PA1
PA1
D5
D5
1
(Continued)
IVCTR0
INTERRUPT SOURCE These four bits indicate the reason why the interrupt was generated
INTERRUPT VECTOR This field defines the port address responsible for generating the
interrupt
D4
PA0
PA0
PA0
D4
1
ISRC3
D3
D3
1
1
0
1
ISRC2
D2
D2
1
0
1
1
60
ISRC1
D1
D1
0
1
1
1
ISRC0
Description
D0
D0
1
1
1
1
First Collision
PA(3 0)
Receive
PA(3 0)
Partition Reconnection
PA(3 0)
No Valid Interrupt
e
e
e
Comments
Collision Port Address
Receive Port Address
Partition Port Address