DP83950BNU NSC [National Semiconductor], DP83950BNU Datasheet - Page 49

• Manufacturer Part Number: DP83950BNU
• Manufacturer: NSC [National Semiconductor]

D(1 0)
D2
D3
D4
D5
D6
D7
6 0 Hub Management Support
Packet Status Register 2
The other registers comprise the remainder of the collision
timer register PSR(3)
ter PSR(6)
Collision Bit Timer
The Collision Timer counts in bit times the time between the
start of repetition of the packet and the detection of the
packet’s first collision The Collision counter increments as
the packet is repeated and freezes when a collision occurs
The value in the counter is only valid when the collision bit
‘‘COL’’ in PSR(1) is set
Repeat Byte Counter
The Repeat Byte Counter is a 16 bit counter which can per-
form two functions In cases where the transmitted packet
possesses an SFD the byte counter counts the number of
received bytes after the SFD field Alternatively if no SFD is
repeated the counter reflects the length of the packet
counted in bytes starting at the beginning of the preamble
field When performing the latter function the counter is
shortened to 7 bits Thus the maximum count value is 127
bytes The mode of counting is indicated by the ‘‘NSFD’’ bit
in PSR(2)
genuinely a Non-SFD packet the status of the COL bit
should be checked During collisions SFD fields may be lost
or created Management software should be robust to this
kind of behaviour
Inter Frame Gap (IFG) Bit Timer
The IFG counter counts in bit times the period in between
repeater transmissions The IFG counter increments when-
ever the RIC is not transmitting a packet If the IFG is long
i e greater than 255 bits the counter sticks at this value
Thus an apparent count value of 255 should be interpreted
as 255 or more bit times
Bit
PSR(4) (5) and the Inter Frame Gap Counter ‘‘IFG’’ regis-
D7
SE
Symbol
CT(9 8)
ELBER
OWC
NSFD
PLER
OWC
D6
JAB
SE
In order to check if the received packet was
NSFD
D5
COLLISION TIMER BITS 9 AND 8 These two bits are the upper bits of the collision bit timer
JABBER EVENT This bit indicates that the receive packet was so long the repeater was forced to go into a
jabber protect condition
ELASTICITY BUFFER ERROR During the packet an Elasticity Buffer under overflow occurred
PHASE LOCK LOOP ERROR The packet suffered sufficient jitter noise corruption to cause the phase
lock loop decoder to lose lock
NON SFD The repeated packet did not contain a Start of Frame Delimiter When this bit is set the Repeat
Byte Counter counts the length of the entire packet When this bit is not set the byte counter only counts
post SFD bytes
Note The operation of this bit is not inhibited by the occurrence of a collision during packet repetition (see description of the
Repeat Byte Counter below)
OUT OF WINDOW COLLISION The packet suffered an out of window collision
SHORT EVENT The receive activity was so small it met the criteria to be classed as a short event
the Repeat Byte Count registers
PLER
D4
ELBER
D3
(Continued)
JAB
D2
49
CBT9
D1
6 4 DESCRIPTION OF HARDWARE
CONNECTION FOR MANAGEMENT INTERFACE
The RIC has been designed so it may be connected to the
Management bus directly or via external bus transceivers
The latter is advantageous in large repeaters In this appli-
cation the system backplane is often heavily loaded beyond
the drive capabilities of the on-chip bus drivers
The uni-directional nature of information transfer on the
MCRS MRXD and MRXC signals means a single open
drain output pin is adequate for each of these signals The
Management Enable (MEN) RIC output pin performs the
function of a drive enable for an external bus transceiver if
one is required
In common with the Inter-RIC bus signals ACTN ANYXN
COLN and IRE the MCRS active level asserted by the
MCRS output is determined by the state of the BINV Mode
Load configuration bit
7 0 Port Block Functions
The RIC has 13 port logic blocks (one for each network
connection) In addition to the packet repetition operations
already described the port block performs two other func-
tions
1 The physical connection to the network segment (trans-
2 It provides a means to protect the network from malfunc-
Each port has its own status register This register allows
the user to determine the current status of the port and
configure a number of port specific functions
Description
ceiver function)
tioning segments (segment partition)
CBT8
D0