LAN9313I SMSC [SMSC Corporation], LAN9313I Datasheet - Page 208

• Manufacturer Part Number: LAN9313I
• Description: Three Port 10/100 Managed Ethernet Switch with MII
• Manufacturer: SMSC [SMSC Corporation]

Revision 1.2 (04-08-08)
13.1.6.2
31:16
15:11
BITS
10:6
5:2
1
0
RESERVED
PHY Address (PHY_ADDR)
These bits select the PHY device being accessed. Refer to
"PHY Addressing," on page 84
assignments.
MII Register Index (MIIRINDA)
These bits select the desired MII register in the PHY. Refer to
"Ethernet PHY Control and Status Registers," on page 231
descriptions on all PHY registers.
RESERVED
MII Write (MIIWnR)
Setting this bit informs the PHY that the access will be a write operation
using the
is cleared, the access will be a read operation, returning data into the
Management Interface Data Register
MII Busy (MIIBZY)
This bit must be read as 0 before writing to the
Data Register (PMI_DATA)
(PMI_ACCESS)
written. During a PHY register access, this bit will be set, signifying a read
or write access is in progress. This is a self-clearing (SC) bit that will return
to 0 when the PHY register access has completed.
During a PHY register write, the
(PMI_DATA)
During a PHY register read, the
(PMI_DATA)
PHY Management Interface Access Register (PMI_ACCESS)
This register is used to control the management cycles to the PHYs. A PHY access is initiated when
this register is written. This register is used in conjunction with the
Register (PMI_DATA)
Note: The Virtual PHY registers are NOT accessible via these registers.
PHY Management Interface Data Register
Offset:
must be kept valid until this bit is cleared.
register is invalid until the MAC has cleared this bit.
registers. This bit is automatically set when this register is
to perform read and write operations to the PHYs.
or
0A8h
DESCRIPTION
PHY Management Interface Access Register
for information on PHY address
PHY Management Interface Data Register
PHY Management Interface Data Register
DATASHEET
(PMI_DATA).
208
PHY Management Interface
Size:
(PMI_DATA). If this bit
for detailed
Section 7.1.1,
Section 13.2,
Three Port 10/100 Managed Ethernet Switch with MII
32 bits
PHY
PHY Management Interface Data
TYPE
R/W
R/W
R/W
SMSC LAN9313/LAN9313i
RO
RO
RO
SC
DEFAULT
00000b
00000b
Datasheet
0b
0b
-
-