LAN9313I SMSC [SMSC Corporation], LAN9313I Datasheet - Page 21

• Manufacturer Part Number: LAN9313I
• Description: Three Port 10/100 Managed Ethernet Switch with MII
• Manufacturer: SMSC [SMSC Corporation]

Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
SMSC LAN9313/LAN9313i
2.2.3
2.2.4
2.2.5
2.2.6
Switch Fabric
The Switch Fabric consists of the following major function blocks:
Ethernet PHYs
The LAN9313/LAN9313i contains three PHYs: Port 1 PHY, Port 2 PHY and a Virtual PHY. The Port 1
& 2 PHYs are identical in functionality and each connect their corresponding Ethernet signal pins to
the switch fabric MAC of their respective port. These PHYs interface with their respective MAC via an
internal MII interface. The Virtual PHY provides the virtual functionality of a PHY and allows connection
of an external MAC to port 0 of the switch fabric as if it was connected to a single port PHY. All PHYs
comply with the IEEE 802.3 Physical Layer for Twisted Pair Ethernet and can be configured for full/half
duplex 100 Mbps (100BASE-TX) or 10Mbps (10BASE-T) Ethernet operation. All PHY registers follow
the IEEE 802.3 (clause 22.2.4) specified MII management register set.
PHY Management Interface (PMI)
The PHY Management Interface (PMI) is used to serially access the internal PHYs as well as the
external PHY on the MII pins (in MAC mode only, see
implements the IEEE 802.3 management protocol, providing read/write commands for PHY
configuration.
SPI/I
This module provides an SPI/I
LAN9313/LAN9313i.
The SPI slave controller allows CPU access to all system CSRs for configuration and management.
The SPI slave controller supports single register and multiple register read and write commands.
Multiple read and multiple write commands support incrementing, decrementing, and static addressing.
10/100 MACs
There is one 10/100 Ethernet MAC per switch fabric port, which provides basic 10/100 Ethernet
functionality, including transmission deferral, collision back-off/retry, TX/RX FCS
checking/generation, TX/RX pause flow control, and transmit back pressure. The 10/100 MACs act
as an interface between the switch engine and the 10/100 PHYs (for ports 1 and 2). The port 0
10/100 MAC interfaces the switch engine to the external MAC/PHY (see
Operation"). Each 10/100 MAC includes RX and TX FIFOs and per port statistic counters.
Switch Engine
This block, consisting of a 3 port VLAN layer 2 switching engine, provides the control for all
forwarding/filtering rules and supports untagged, VLAN tagged, and priority tagged frames. The
switch engine provides an extensive feature set which includes spanning tree protocol support,
multicast packet filtering and Quality of Service (QoS) packet prioritization by VLAN tag, destination
address, and port default value or DIFFSERV/TOS, allowing for a range of prioritization
implementations. A 1K entry forwarding table provides ample room for MAC address forwarding
tables.
Buffer Manager
This block controls the free buffer space, multi-level transmit queues, transmission scheduling, and
packet dropping of the switch fabric. 32K of buffer RAM allows for the storage of multiple packets
while forwarding operations are completed. Each port is allocated 1a cluster of 4 dynamic QoS
queues which allow each queue size to grow and shrink with traffic, effectively utilizing all available
memory. This memory is managed dynamically via the Buffer Manager block.
Switch CSRs
This block contains all switch related control and status registers, and allows all aspects of the
switch fabric to be managed. These registers are indirectly accessible via the system control and
status registers
2
C Slave Controller
2
C slave interface which can be used for CPU serial management of the
DATASHEET
21
Section 2.3, "Modes of
Section 2.3, "Modes of
Operation"). The PMI
Revision 1.2 (04-08-08)