STA333BW_11 STMICROELECTRONICS [STMicroelectronics], STA333BW_11 Datasheet - Page 19

• Manufacturer Part Number: STA333BW_11
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STA333BW
5.3
5.3.1
5.3.2
5.4
5.4.1
5.4.2
5.4.3
Write operation
Following the START condition the master sends a device select code with the RW bit set
to 0. The STA333BW acknowledges this and then waits for the byte of internal address.
After receiving the internal byte address the STA333BW again responds with an
acknowledgement.
Byte write
In the byte write mode the master sends one data byte, this is acknowledged by the
STA333BW. The master then terminates the transfer by generating a STOP condition.
Multi-byte write
The multi-byte write modes can start from any internal address. The master generating a
STOP condition terminates the transfer.
Figure 8.
Read operation
Current address byte read
Following the START condition the master sends a device select code with the RW bit set
to 1. The STA333BW acknowledges this and then responds by sending one byte of data.
The master then terminates the transfer by generating a STOP condition.
Current address multi-byte read
The multi-byte read modes can start from any internal address. Sequential data bytes are
read from sequential addresses within the STA333BW. The master acknowledges each
data byte read and then generates a STOP condition terminating the transfer.
Random address byte read
Following the START condition the master sends a device select code with the RW bit set
to 0. The STA333BW acknowledges this and then the master writes the internal address
byte. After receiving, the internal byte address the STA333BW again responds with an
acknowledgement. The master then initiates another START condition and sends the device
select code with the RW bit set to 1. The STA333BW acknowledges this and then responds
by sending one byte of data. The master then terminates the transfer by generating a STOP
condition.
MULTIBYTE
WRITE
WRITE
BYTE
START
START
Write mode sequence
DEV-ADDR
DEV-ADDR
RW
RW
ACK
ACK
Doc ID 13773 Rev 3
SUB-ADDR
SUB-ADDR
ACK
ACK
DATA IN
DATA IN
ACK
ACK
STOP
I
2
C bus specification
DATA IN
ACK
STOP
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