STA333BW_11 STMICROELECTRONICS [STMicroelectronics], STA333BW_11 Datasheet - Page 39

• Manufacturer Part Number: STA333BW_11
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STA333BW
Invalid input detect mute enable
Table 44.
Setting the IDE bit enables this function, which looks at the input I
mutes if the signals are perceived as invalid.
Binary output mode clock loss detection
Table 45.
Detects loss of input MCLK in binary mode and will output 50% duty cycle.
LRCK double trigger protection
Table 46.
LDTE, when enabled, prevents double trigger of LRCLK on instable I2S input.
Auto EAPD on clock loss
Table 47.
When active, issues a power device power down signal (EAPD) on clock loss detection.
IC power down
Table 48.
2
3
4
5
6
Bit
Bit
Bit
Bit
Bit
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Invalid input detect mute enable
Binary output mode clock loss detection
LRCK double trigger protection
Auto EAPD on clock loss
IC power down
1
1
1
0
1
RST
RST
RST
RST
RST
IDE
BCLE
LDTE
ECLE
PWDN
Doc ID 13773 Rev 3
Name
Name
Name
Name
Name
0: disables the automatic invalid input detect mute
1: enables the automatic invalid input detect mute
0: binary output mode clock loss detection disabled
1: binary output mode clock loss detection enable
0: LRCLK double trigger protection disabled
1: LRCLK double trigger protection enabled
0: auto EAPD on clock loss not enabled
1: auto EAPD on clock loss
0: IC power down low-power condition
1: IC normal operation
Description
Description
Description
Description
Description
2
S data and automatically
Register description
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