HMP8112CN HARRIS [Harris Corporation], HMP8112CN Datasheet - Page 13

• Manufacturer Part Number: HMP8112CN
• Description: NTSC/PAL Video Decoder
• Manufacturer: HARRIS [Harris Corporation]

Reset
The RESET pin is used to return the decoder to an initializa-
tion state. This pin should be used after a power-up to set
the part into a known state. The internal registers are
returned to their RESET state and the Serial I
returned to inactive state. The RESET pin is an active low
signal and should be asserted for minimum of 1 CLK cycle.
After a RESET or a software reset has occurred all output
pins are three-stated. The following pins must be pulled high
to ensure proper operation:
NOTES:
/
1. Y0 is the first active luminance pixel of a line. Cb0 and Cr0 are first active chrominance pixels in a line. Cb and Cr will alternate every cycle
2. Active is asserted for lines 22-262.5 and 285.5-525. DVLD is asserted for every valid pixel during both active and blanking regions. DVLD
ACTIVE
DVLDY
due to the 4:2:2 subsampling.
is asserted during vertical and horizontal sync.
Y[7-0]
CLK
<- PIXEL 0
CbCr[7-0]
ACTIVE
Y[7-0]
DVLD
CLK
NTSC M, N PAL M
LINES 22-263.5
LINES 1-21
t
t
DVLD
DLY
t
t
DVLD
(PAL B, D, G, H, I, N COMB N)
(LINES 1-23.5)
(LINES 23.5-310)
DLY
PIXEL 1
Cb
FIGURE 15B. ACTIVE VIDEO REGIONS IN 16-BIT MODE
0
FIGURE 15A. OUTPUT TIMING 16-BIT MODE
FIGURE 16. OUTPUT TIMING 8-BIT MODE
PIXEL 2
Y
0
Y
Cr
2
N
N
C port is
PIXEL 3
NOTE 2
NOTE 1
Cr
HMP8112
0
13
PIXEL N-3
A 10K or smaller pullup resistor to V
Y
1
Y
Cb
0
<- PIXEL 0
0
PIXEL N-2
Cb
Y
Cr
NTSC M, N PAL M
2
1
LINES 263.5-284
0
LINES 285-525
PIXEL N-1
Y
2
HSYNC
VSYNC
DVLD
ACTIVE
FIELD
PIXEL N
Cr
(PAL B, D, G, H, I, N COMB N)
(LINES 311-335)
(LINES 336-623.5)
Y
Cb
2
2
1
CC
is recommended.