HMP8112CN HARRIS [Harris Corporation], HMP8112CN Datasheet - Page 19

• Manufacturer Part Number: HMP8112CN
• Description: NTSC/PAL Video Decoder
• Manufacturer: HARRIS [Harris Corporation]

NUMBER
NUMBER
NUMBER
NUMBER
15 - 10
15 - 10
6, 5, 4
9 - 8
7 - 0
9 - 8
BIT
BIT
BIT
BIT
7
3
2
Not Used
DC Restore
Programmable Start
Time
DC Restore
Programmable End
Time
Not Used
DC Restore
Programmable End
Time
Square Pixel/ITU-R
BT601 Select
Output Field Control
“FLD_CONT(2-0)”
8/16 output Select
OEN
FUNCTION
FUNCTION
FUNCTION
FUNCTION
This register provides a programmable delay for the internal DC RES signal. The start
time of the DC RES pulse is set from the detection of horizontal sync in the video data.
DC RES is programmable in CLK increments and has a fixed 1 clock delay following the
falling edge of horizontal sync. This is the upper byte of the 10-bit word.
This register provides a programmable delay for the internal DC RES signal. The end
time of the DC RES pulse is set from the detection of horizontal sync in the video data.
DC RES is programmable in CLK increments and has a fixed 1 clock delay following the
falling edge of horizontal sync. This signal is used to run the GATE B pin of the A/D con-
verter. This is the lower byte of the 10-bit word.
This register provides a programmable delay for the external DC RES signal. The end
time of the DC RES pulse is set from the detection of horizontal sync in the video data.
DC RES is programmable in CLK increments and has a fixed 1 clock delay following the
falling edge of horizontal sync. This is the upper byte of the 10-bit word.
When “1”, Square pixel output is selected, when “0” ITU-R BT601 output rate is selected.
These bits control the field capture rate of the HMP8112. The user can select every 4th
field, every other field or every field of video to be output to the data port.
000 = No Capture Enabled
001 = Capture every 4th field
010 = Capture every 2nd field
011 = Capture every 2nd odd field
100 = Capture every 2nd even field
101 = Capture every odd field
110 = Capture every even field
111 = Capture all fields
When “1”, the 8-bit Burst Transfer output mode is selected. When “0”, the 16-bit Synchro-
nous Pixel Transfer output mode is selected.
This bit enables the Y(7-0), CbCr(7-0), ACTIVE, HSYNC, VSYNC and DVLD outputs.
1 = Outputs enabled; 0 = three-stated.
TABLE 28. OUTPUT FORMAT CONTROL REGISTER
TABLE 25. DC RESTORE START TIME REGISTER
TABLE 26. DC RESTORE END TIME REGISTER
TABLE 27. DC RESTORE END TIME REGISTER
DESTINATION ADDRESS = 13
DESTINATION ADDRESS = 14
DESTINATION ADDRESS = 15
DESTINATION ADDRESS = 16
HMP8112
19
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
H
H
H
H
0101 0010
XXXX XX
XXXX XX
RESET
RESET
RESET
RESET
STATE
STATE
STATE
STATE
000
00
00
0
0
0
B
B
B
B
B
B
B