HMP8112CN HARRIS [Harris Corporation], HMP8112CN Datasheet - Page 22

• Manufacturer Part Number: HMP8112CN
• Description: NTSC/PAL Video Decoder
• Manufacturer: HARRIS [Harris Corporation]

Pin Description
CCLAMP_CAP
LCLAMP_CAP
GAIN_CTRL
LAGC_CAP
CbCr[0:7]
LIN[0:2]
L_ADIN
HSYNC
DEC_T
RESET
DEC_L
L_OUT
NAME
Y[0:7]
DVLD
WPE
SDA
SCL
CLK
CIN
54-58, 60, 63,
PQFP PIN
42, 43, 45,
NUMBER
5, 6, 7
13, 38
47-51
19
27
28
78
30
77
76
29
40
41
34
64
66
71
8
9
OUTPUT
INPUT/
Output
Output
Output
Output
Output
Output
Input/
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Analog Video Inputs. Inputs 0 and 1 are composite inputs. Input 2 can be either a
composite input or the Y component of an S-Video signal.
Analog Chroma input component of an S-Video Input.
White Peak Enable. When enabled (‘1’), the video amplifiers gain is reduced when
the digital output code exceeds 248. When disabled (‘0’) the video amplifier will clip
when the A/D reaches code 255.
Gain Control Input. DC voltage to set the video amplifier’s gain.
Decoupling for A/D Converter Reference. Connect a 0.01 F and 0.1 F capacitors to
AGND.
Decoupling for A/D Converter Reference. Connect a 0.01 F and 0.1 F capacitors to
AGND.
Capacitor Connection for Luminance AGC Circuit. Controls the AGC loop time con-
stant.
Capacitor Connection for Luminance Clamp Circuit. Controls the clamp loop time
constant.
Capacitor Connection for Chrominance Clamp Circuit. Controls the clamp loop time
constant.
Luminance A/D Converters input from antialiasing filter.
Luminance or Composite Analog Video Amplifier output to antialiasing filter.
The serial I
The serial I
Master clock for the decoder. This clock is used to run the internal logic, A/D convert-
ers, and Phase Locked Loops. All I/O pins (except the I
master clock. A 50ppmcrystal should be used with a waveform symmetry of 60/40%
or better.
Asynchronous Reset pin. Master Chip reset to initialize the internal states and set
the internal registers to a known state.
CbCr Data Output Port. The chrominance data output port of the decoder. Data is in
unsigned format and can range from 0 to 255. The CbCr data is subsampled to 4:2:2
format. In 4:2:2 format the CbCr bus toggles between Cb and Cr samples with the
first sample of a line always being Cb. The port is designed to minimize external logic
needed to interface to a VRAM Serial Access Port, DRAM or FIFO.
Y Data Output Port. The luminance data output port of the decoder. Data is in un-
signed format and can range from 16 to 255. The port is designed to minimize exter-
nal logic needed to interface to a VRAM Serial Access Port, DRAM or FIFO.
Data Valid. This pin signals when valid data is available on the data output ports. This
pin is three-stated after a RESET or software reset and should be pulled high
through a 10K resistor.
Horizontal Sync. This video synchronous pulse is generated by the detection of hor-
izontal sync on the video input. In the absence of video, the HSYNC rate is set when
the internal PLL counters overflow. The HSYNC begin and end time can be pro-
grammed and is synchronous to CLK. This pin is three-stated after a RESET or soft-
ware reset and should be pulled high through a 10K resistor.
HMP8112
2
2
C serial input/output data line.
C serial bus clock line.
22
DESCRIPTION
2
C) are synchronous to this