HMP8112CN HARRIS [Harris Corporation], HMP8112CN Datasheet - Page 17

• Manufacturer Part Number: HMP8112CN
• Description: NTSC/PAL Video Decoder
• Manufacturer: HARRIS [Harris Corporation]

NUMBER
NUMBER
NUMBER
NUMBER
NUMBER
15 - 10
15 - 10
9 - 8
7 - 0
9 - 8
7 - 0
9 - 8
BIT
BIT
BIT
BIT
BIT
Horizontal AGC
Pulse Programmable
Start Time
Horizontal AGC
Pulse Programmable
End Time
Not Used
Horizontal AGC
Pulse Programmable
End Time
Horizontal Drive
Programmable Start
Time
Not Used
Horizontal Drive
Programmable Start
Time
FUNCTION
FUNCTION
FUNCTION
FUNCTION
FUNCTION
TABLE 15. HORIZONTAL AGC START TIME REGISTER (Continued)
This register provides a programmable delay for the HAGC pulse that control the sync
tip AGC in the A/D converters. The start time of the HAGC pulse is set from the detection
of horizontal sync in the video data. HAGC is programmable in CLK increments and has
a fixed 1 clock delay following the falling edge of horizontal sync. This is the upper byte
of the 10-bit word.
This register provides a programmable delay for the HAGC pulse that control the sync
tip AGC in the A/D converters. The end time of the HAGC pulse is set from the detection
of horizontal sync in the video data. HAGC is programmable in CLK increments and has
a fixed 1 clock delay following the falling edge of horizontal sync. This is the lower byte
of the 10-bit word.
Write Ignored, Read 0’s
This register provides a programmable delay for the HAGC pulse that control the sync
tip AGC in the A/D converters. The end time of the HAGC pulse is set from the detection
of horizontal sync in the video data. HAGC is programmable in CLK increments and has
a fixed 1 clock delay following the falling edge of horizontal sync. This is the upper byte
of the 10-bit word.
This register provides a programmable delay for the external HDRIVE signal. The start
time of the HDRIVE pulse is set from the detection of horizontal sync in the video data.
HDRIVE is programmable in CLK increments and has a fixed 1 clock delay following the
falling edge of horizontal sync. This is the lower byte of the 10-bit word.
Write Ignored, Read 0’s
This register provides a programmable delay for the external HDRIVE signal. The start
time of the HDRIVE pulse is set from the detection of horizontal sync in the video data.
HDRIVE is programmable in CLK increments and has a fixed 1 clock delay following the
falling edge of horizontal sync. This is the upper byte of the 10-bit word.
TABLE 18. HORIZONTAL SYNC START TIME REGISTER
TABLE 19. HORIZONTAL SYNC START TIME REGISTER
TABLE 16. HORIZONTAL AGC END TIME REGISTER
TABLE 17. HORIZONTAL AGC END TIME REGISTER
DESTINATION ADDRESS = 0A
DESTINATION ADDRESS = 0B
DESTINATION ADDRESS = 0C
DESTINATION ADDRESS = 0D
DESTINATION ADDRESS = 09
HMP8112
17
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
H
H
H
H
H
0000 0000
0011 1011
XXXX XX
XXXX XX
RESET
STATE
RESET
STATE
RESET
STATE
RESET
STATE
RESET
STATE
11
00
11
B
B
B
B
B