HMP8112CN HARRIS [Harris Corporation], HMP8112CN Datasheet - Page 23

• Manufacturer Part Number: HMP8112CN
• Description: NTSC/PAL Video Decoder
• Manufacturer: HARRIS [Harris Corporation]

Pin Description
A/D TEST
ACTIVE
VSYNC
NAME
FIELD
DGND
AGND
DV
TEST
AV
NC
CC
CC
52, 59, 68, 75,
25, 32, 33, 35,
39, 46, 53, 61,
62, 69, 72, 73,
26, 31,37, 44,
15,16, 21, 22,
4, 18, 20, 74
1, 3, 10, 11,
PQFP PIN
NUMBER
2, 12,14
23, 24
(Continued)
70
67
65
36
79
80
17
OUTPUT
INPUT/
Output
Output
Output
Output
Input
Input
Input
Input
Input
NA
Vertical Sync. This video synchronous pulse is generated by the detection of a vertical
sync on the video input. In the absence of video the VSYNC rate is set by the over flow
of the internal line rate counter. This pin is three-stated after a RESET or software reset
and should be pulled high through a 10K resistor.
Field Flag. When set (‘0’) this signals that an ODD field is presently being output from
the decoder. When cleared (‘1’) this signals an EVEN field. This flag will toggle when
no vertical sync is detected and 337 lines have elapsed. This pin is three-stated after
a RESET or software reset and should be pulled high through a 10K resistor.
Active Video Flag. This flag is asserted (‘1’) when the active portion of the video line
is available on the output port. This signal is always set during Burst Output data
mode. This flag is free running and synchronous to CLK. This pin is three-stated after
a RESET or software reset and should be pulled high through a 10K resistor.
Test input. This pin is used for production test and should be connected to digital
ground.
5V Logic Supply Pins
Digital Ground Pins
5V Analog Supply Pins
Analog GND
A/D Test Pin. This pin should be left open.
No Connect. These pins should be left open.
HMP8112
23
DESCRIPTION