HYB18H512321BF-08/10 QIMONDA [Qimonda AG], HYB18H512321BF-08/10 Datasheet - Page 33

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HYB18H512321BF-08/10

Manufacturer Part Number
HYB18H512321BF-08/10
Description
512-Mbit GDDR3 Graphics RAM
Manufacturer
QIMONDA [Qimonda AG]
Datasheet
Notes
1. 0 °C
2. Data Bus consists of DQ, DM, WDQS.
3. Definitions for IDD:
Rev. 1.1, 2007-09
05292007-WAU2-UU95
LOW is defined as VIN = 0.4
TABLE is defined as inputs are stable at a HIGH level.
SWITCHING is defined as inputs are changing between HIGH and LOW every clock cycle for address and control signals,
and inputs changing 50% of each data transfer for DQ signals.
Tc
85 °C
×
VDDQ; HIGH is defined as
33
V
IN
=
V
DDQ
;
Internet Data Sheet
HYB18H512321BF
512-Mbit GDDR3

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