HYB18H512321BF-08/10 QIMONDA [Qimonda AG], HYB18H512321BF-08/10 Datasheet - Page 36

• Manufacturer Part Number: HYB18H512321BF-08/10
• Description: 512-Mbit GDDR3 Graphics RAM
• Manufacturer: QIMONDA [Qimonda AG]

1) DLL on mode ( -8/10/-11/-12/-14
2)
3) This value of tMRD applies only to the case where the “DLL reset” bit is not activated
4)
5)
6)
7)
8) WTR and
9) Please round up
10) This parameter is defined per byte
Rev. 1.1, 2007-09
05292007-WAU2-UU95
Parameter
Delay from AREF to next
ACT/ AREF
Self Refresh Exit time
Power Down Exit time
Other Timing Parameters
RES to CKE setup timing
RES to CKE hold timing
Termination update Keep
Out timing
Rev. ID EMRS to DQ on
timing
Rev. ID EMRS to DQ off
timing
t
t
t
t
t
HP
MRD
RASmax
RCDWR(Min)
CCD
is the lesser of
is either for gapless consecutive reads or gapless consecutive writes. BL =4
is defined from MRS to any other command then READ
is 8×
t
may not drop below 2 ×
WR
t
REF
start at the first rising edge of CLK after the last valid (falling) WDQS edge of the slowest WDQS signal
CAS latency Symbol
t
RTW
t
CL
minimum and
to the next integer of
t
t
t
t
t
t
t
t
RFC
XSC
XPN
ATS
ATH
KO
RIDon
RIDoff
f
CK(Min)
t
CK
t
CH
minimum actually applied to the device CLK, CLK inputs
= 400 MHz)
-8
Min
52.0
1000 —
7
10
10
10
—
—
t
CK
Max
—
—
—
—
—
20
20
–10
Min. Max. Min. Max. Min. Max. Min.
52.0
1000 —
7
10
10
10
—
—
36
—
—
—
—
—
20
20
Limit Values
–11
52.0
1000 —
7
10
10
10
—
—
—
—
—
—
—
20
20
–12
1000 —
7
10
10
10
—
—
52.0
—
—
—
—
—
20
20
–14
52.0
1000 —
6
10
10
10
—
—
Internet Data Sheet
HYB18H512321BF
—
—
—
—
—
20
20
Max.
512-Mbit GDDR3
Unit Note
ns
t
t
ns
ns
ns
ns
ns
CK
CK