HYB18H512321BF-08/10 QIMONDA [Qimonda AG], HYB18H512321BF-08/10 Datasheet - Page 34

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HYB18H512321BF-08/10

Manufacturer Part Number
HYB18H512321BF-08/10
Description
512-Mbit GDDR3 Graphics RAM
Manufacturer
QIMONDA [Qimonda AG]
Datasheet
5.12
Rev. 1.1, 2007-09
05292007-WAU2-UU95
Parameter
Clock and Clock Enable
System
frequency
Clock high level width
Clock low-level width
Minimum clock half period
Command and Address Setup and Hold Timing
Address/Command input
setup time
Address/Command input
hold time
Address/Command input
pulse width
Mode Register Set Timing
Mode Register Set cycle time
Mode Register Set to READ
timing
Row Timing
Row Cycle Time
Row Active Time
ACT(a) to ACT(b) Command
period
Row Precharge Time
Row to Column Delay Time
for Reads
Row to Column Delay Time
for Writes
Four Active Windows within
Rank
CAS latency Symbol
CL=13
CL= 12
CL= 11
CL =10
CL = 9
CL = 8
CL = 7
AC Timings for HYB18H512321BF
f
f
f
f
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CK13
CK12
CK11
CK10
CK9
CK8
CK7
CH
CL
HP
IS
IH
IPW
MRD
MRDR
RC
RAS
RRD
RP
RCDRD
RCDWR
FAW
-8
Min
700
450
400
400
400
400
400
0.45
0.45
0.45
0.22
0.22
0.7
6
12
40
25
10
15
14
40
Max
1200 —
1000 450
900
800
700
600
550
0.55
0.55
t
RCDWR(Min)
–10
Min. Max. Min. Max. Min. Max. Min.
400
400
400
400
400
0.45
0.45
0.45
0.24
0.24
0.7
6
12
37
23
9
14
13
36
34
= max(
1000 —
900
800
700
600
550
0.55
0.55
t
Limit Values
RCDRD(Min)
–11
400
400
400
400
400
0.45
0.45
0.45
0.27
0.27
0.7
6
12
35
22
8
13
12
32
Timing Parameters for HYB18H512321BF
900
800
700
600
550
0.55
0.55
- (WL + 1) ×
–12
400
400
400
400
400
0.45
0.45
0.45
0.7
6
12
34
21
8
13
12
32
0.3
0.3
800
700
650
550
500
0.55
0.55
t
CK
;2×
t
–14
400
400
400
400
400
0.45
0.45
0.45
0.35
0.35
0.7
6
12
30
18
7
12
11
28
CK
)
Internet Data Sheet
HYB18H512321BF
700
650
600
500
450
0.55
0.55
Max.
512-Mbit GDDR3
TABLE 22
Unit Note
MHz
MHz
MHz
MHz
MHz
MHz
MHz
t
t
t
ns
ns
t
t
t
t
t
t
t
t
t
t
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
1)
1)
1)
1)
1)
1)
2)
3)4)
5)
6)

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