MC9S08GT16 MOTOROLA [Motorola, Inc], MC9S08GT16 Datasheet - Page 122

• Manufacturer Part Number: MC9S08GT16
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Internal Clock Generator (ICG) Module
ICGIF — ICG Interrupt Flag
7.5.4
DCOS — DCO Clock Stable
7.5.5
122
The ICGIF read/write flag is set when an ICG interrupt request is pending. It is cleared by a reset or
by reading the ICG status register when ICGIF is set and then writing a 1 to ICGIF. If another ICG
interrupt occurs before the clearing sequence is complete, the sequence is reset so ICGIF would remain
set after the clear sequence was completed for the earlier interrupt. Writing a 0 to ICGIF has no effect.
The DCOS bit is set when the DCO clock (ICG2DCLK) is stable, meaning the count error has not
changed by more than n
used when exiting off state if CLKS = X1 to determine when to switch to the requested clock mode. It
is also used in self-clocked mode to determine when to start monitoring the DCO clock. This bit is
cleared upon entering the off state.
1 = An ICG interrupt request is pending.
0 = No ICG interrupt request is pending.
1 = DCO clock is stable.
0 = DCO clock is unstable.
ICG Status Register 2 (ICGS2)
ICG Filter Registers (ICGFLTU, ICGFLTL)
Reset:
Reset:
Read:
Write:
Read:
Write:
unlock
Figure 7-17. ICG Upper Filter Register (ICGFLTU)
Bit 15
Bit 7
0
0
0
0
Figure 7-16. ICG Status Register 2 (ICGS2)
for two consecutive samples and the DCO clock is not static. This bit is
= Unimplemented or Reserved
= Unimplemented or Reserved
MC9S08GB/GT Data Sheet, Rev. 2.3
14
6
0
0
0
0
13
5
0
0
0
0
12
4
0
0
0
0
11
3
0
0
0
10
2
0
0
0
FLT
Freescale Semiconductor
1
0
0
0
9
DCOS
Bit 0
Bit 8
0
0