MC9S08GT16 MOTOROLA [Motorola, Inc], MC9S08GT16 Datasheet - Page 255

• Manufacturer Part Number: MC9S08GT16
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

RWAEN — Enable R/W for Comparator A
RWB — R/W Comparison Value for Comparator B
RWBEN — Enable R/W for Comparator B
15.5.3.8 Debug Trigger Register (DBGT)
This register can be read any time, but may be written only if ARM = 0, except bits 4 and 5 are hard-wired
to 0s.
TRGSEL — Trigger Type
BEGIN — Begin/End Trigger Select
Freescale Semiconductor
Controls whether the level of R/W is considered for a comparator A match.
When RWBEN = 1, this bit determines whether a read or a write access qualifies comparator B. When
RWBEN = 0, RWB and the R/W signal do not affect comparator B.
Controls whether the level of R/W is considered for a comparator B match.
Controls whether the match outputs from comparators A and B are qualified with the opcode tracking
logic in the debug module. If TRGSEL is set, a match signal from comparator A or B must propagate
through the opcode tracking logic and a trigger event is only signalled to the FIFO logic if the opcode
at the match address is actually executed.
Controls whether the FIFO starts filling at a trigger or fills in a circular manner until a trigger ends the
capture of information. In event-only trigger modes, this bit is ignored and all debug runs are assumed
to be begin traces.
1 = R/W is used in comparison A.
0 = R/W is not used in comparison A.
1 = Comparator B can match only on a read cycle.
0 = Comparator B can match only on a write cycle.
1 = R/W is used in comparison B.
0 = R/W is not used in comparison B.
1 = Trigger if opcode at compare address is executed (tag).
0 = Trigger on access to compare address (force).
1 = Trigger initiates data storage (begin trace).
0 = Data stored in FIFO until trigger (end trace).
Reset:
Read:
Write:
TRGSEL
Bit 7
0
Figure 15-8. Debug Trigger Register (DBGT)
= Unimplemented or Reserved
MC9S08GB/GT Data Sheet, Rev. 2.3
BEGIN
6
0
5
0
0
4
0
0
TRG3
3
0
TRG2
2
0
Registers and Control Bits
TRG1
1
0
TRG0
Bit 0
0
255