MC9S08GT16 MOTOROLA [Motorola, Inc], MC9S08GT16 Datasheet - Page 65

• Manufacturer Part Number: MC9S08GT16
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

5.5.2.2
The IRQMOD control bit re-configures the detection logic so it detects edge events and pin levels. In this
edge detection mode, the IRQF status flag becomes set when an edge is detected (when the IRQ pin
changes from the deasserted to the asserted level), but the flag is continuously set (and cannot be cleared)
as long as the IRQ pin remains at the asserted level.
5.5.3
Table 5-1
bottom of the table. The high-order byte of the address for the interrupt service routine is located at the
first address in the vector address column, and the low-order byte of the address for the interrupt service
routine is located at the next higher address.
When an interrupt condition occurs, an associated flag bit becomes set. If the associated local interrupt
enable is 1, an interrupt request is sent to the CPU. Within the CPU, if the global interrupt mask (I bit in
the CCR) is 0, the CPU will finish the current instruction, stack the PCL, PCH, X, A, and CCR CPU
registers, set the I bit, and then fetch the interrupt vector for the highest priority pending interrupt.
Processing then continues in the interrupt service routine.
Freescale Semiconductor
provides a summary of all interrupt sources. Higher-priority sources are located toward the
Interrupt Vectors, Sources, and Local Masks
Edge and Level Sensitivity
The voltage measured on the pulled up IRQ pin may be as low as V
V. The internal gates connected to this pin are pulled all the way to V
other pins with enabled pullup resistors will have an unloaded measurement
of V
DD
.
MC9S08GB/GT Data Sheet, Rev. 2.3
NOTE
DD
DD
– 0.7
. All
Interrupts
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