RG82845M Intel, RG82845M Datasheet - Page 115

• Manufacturer Part Number: RG82845M
• Description: Chipset Memory Controller Hub Mobile
• Manufacturer: Intel

5.1.3.
5.2.
5.2.1.
250687-002
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In an Intel 845MP/845MZ Chipset platform and its interrupts are generated as upstream hub interface
Memory Writes. Furthermore, PCI 2.2 defines MSI’s (Message Signaled Interrupts) that are also in the
form of Memory Writes. A PCI 2.2 device may generate an interrupt as an MSI cycle on it’s PCI bus.
The MSI may be directed directly to the System bus. The target of an MSI is dependent on the address of
the interrupt Memory Write. The Intel 845MP/845MZ Chipset MCH-M forwards inbound hub interface
and AGP (PCI semantic only) Memory Writes to address 0FEEx_xxxxh, to the System bus as “Interrupt
Message Transactions”.
Upstream Interrupt Messages
The MCH-M accepts message based interrupts from AGP (PCI semantics only) or its hub interface and
forwards them to the System bus as Interrupt Message Transactions. The interrupt messages presented to
the MCH-M are in the form of Memory Writes to address 0FEEx_xxxxh. At the hub interface or AGP
interface the Memory Write interrupt message is treated like any other Memory Write; it is either posted
into the inbound data buffer (if space is available) or retried (if data buffer space is not immediately
available). Once posted, the Memory Write from AGP or the hub interface, to address 0FEEx_xxxxh, is
decoded as a cycle that needs to be propagated by the MCH-M to the System bus as an Interrupt
Message Transaction.
System Memory Interface
DDR Interface Overview
The Intel 845MP Chipset MCH-M supports DDR at 200 and 266 MHz and includes support for:
The Intel 845MZ Chipset MCH-M supports DDR at 200 MHz and includes support for:
The 2 bank select lines SBS[1:0] and the 13 Address lines SMA[12:0] allow the Intel 845MP/845MZ
MCH-M to support 64 bit wide SO-DIMMs using 64-Mb, 128-Mb, 256-Mb, and 512-Mb DDR
technology. While address lines SMA[9:0] determine the starting address for a burst, burst lengths can
be 2, 4, or 8. Four chip selects SCS# lines allow a maximum of two rows of single-sided DDR SO-
DIMMs and four rows of double-sided DDR SO-DIMMs.
Intel 845MP/845MZ main memory controller targets CAS latencies of 2 and 2.5 for DDR. Intel
845MP/845MZ provides refresh functionality with a programmable rate (normal DDR rate is 1
refresh/15.6 us). For write operations of less than a Qword in size, the MCH-M will perform a byte-wise
write.
• Up to 1 GB of PC2100 DDR
• PC2100, unbuffered, 200-pin DDR SO-DIMMs
• Maximum of 2 SO-DIMMs, Single-sided and/or Double-sided b
• Configurable optional ECC
• Up to 512 MB of PC1600 DDR
• PC1600, unbuffered, 200-pin DDR SO-DIMMs
• Maximum of 2 SO-DIMMs, Single-sided and/or Double-sided
• Configurable optional ECC
Datasheet
Intel
®
82845MP/82845MZ Chipset-Mobile (MCH-M)
115