RG82845M Intel, RG82845M Datasheet - Page 23

• Manufacturer Part Number: RG82845M
• Description: Chipset Memory Controller Hub Mobile
• Manufacturer: Intel

2.2.
250687-002
Table 5. DDR Interface Signal Descriptions
R
SDQS[8:0]
DDR Interface
SCS#[3:0]
SMA[12:0]
SBS[1:0]
SRAS#
SCAS#
SWE#
SDQ[63:0]
SCB[7:0]
SCKE[3:0]
RCVENOUT#
RCVENIN#
Signal Name
CMOS 2X
CMOS 2X
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Type
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
I
Chip Select: These pins select the particular DDR components during the active
state.
Note: There is one SCS# per DDR-SDRAM Physical SO-DIMM device row. These
signals can be toggled on every rising System Memory Clock edge.
Multiplexed Memory Address: These signals are used to provide the multiplexed
row and column address to DDR.
DDR Row Address Strobe: SRAS# may be heavily loaded and requires 2 DDR
clock cycles for setup time to the DDRs: Used with SCAS# and SWE# (along with
SCS#) to define the DRAM commands.
DDR Column Address Strobe: SCAS# may be heavily loaded and requires 2 DDR
clock cycles for setup time to the DDRs. Used with SRAS# and SWE# (along with
SCS#) to define the DRAM commands.
Write Enable: Used with SCAS# and SRAS# (along with SCS#) to define the
DRAM commands. SWE# is asserted during writes to DDR. SWE# may be heavily
loaded and requires 2 DDR clock cycles for setup time to the DDRs.
Data Lines: These signals are used to interface to the DDR data bus.
Data Lines: These signals are used to interface to the SDRAM ECC signals (to be
used if SO-DIMMs support ECC).
Data Strobes:
There is an associated data strobe (DQS) for each data strobe (DQ) and check
bit (CB) group.
SDQS8 -> SCB[7:0]
SDQS7 -> SDQ[63:56]
SDQS6 -> SDQ[55:48]
SDQS5 -> SDQ[47:40]
SDQS4 -> SDQ[39:32]
SDQS3 -> SDQ[31:24]
SDQS2 -> SDQ[23:16]
SDQS1 -> SDQ[15:8]
SDQS0 -> SDQ[7:0]
Clock Enable: These pins are used to signal a self-refresh or power down
command to a DDR array when entering system suspend. SCKE is also used to
dynamically power down inactive DDR rows. There is one SCKE per DDR row.
These signals can be toggled on every rising SCLK edge.
Clock Output: Used to emulate source-synch clocking for reads. Connects to
RCVENIN#.
Clock Input: Used to emulate source-synch clocking for reads. Connects to
RCVENOUT#.
Memory Bank Address: These signals define the banks that are selected within
each DDR row. The SMA and SBS signals combine to address every possible
location within a DDR device.
Datasheet
Intel
®
82845MP/82845MZ Chipset-Mobile (MCH-M)
Description
23