SCD1283 INTEL [Intel Corporation], SCD1283 Datasheet - Page 31

• Manufacturer Part Number: SCD1283
• Description: IEEE 1284-Compatible Parallel Interface
• Manufacturer: INTEL [Intel Corporation]

Datasheet
Figure 6. Control Signal Generation
Table 6. LIVR[2:0] Encoding
CONTROL
ADDRESS
CPU I/O
CPU
A direction change (DirCh) interrupt occurs when the remote master has reversed the interface
from ECP forward to ECP reverse or ECP reverse to ECP forward. The IDReq interrupt is
generated when the remote master issues an ID Request command during IEEE 1284 negotiations.
The normal response by the local CPU is to send its ID string after reversing the direction of the
data pipeline by setting the DMAdir bit to ‘1’.
If vectored interrupts are required by the system, then the LIVR must be initialized by the local
CPU. The upper five bits are defined by the local CPU and can be any value appropriate to the
system design. The lower three bits should be initialized to zero during the programming of the
LIVR, however they are ‘don’t cares’ and masked in the PIVR to provide the vector indicating the
source, and type of request from the parallel channel.
Access to the parallel channel LIVR is made by first setting the AER to ‘x’00’, making the Channel
Zero register set accessible. Since the LIVR is a read/write register, the local CPU can read it at any
time. When read during a normal read cycle, the upper 5 bits return the original value loaded by the
CPU.
The three least-significant bits always ready back as the current service-request status of the
parallel port if an interrupt is in progress; otherwise they read back as ‘0’. The encoding of the three
least-significant bits of LIVR during a service acknowledge cycle indicates which of the functional
blocks in the parallel channel is requesting service as shown in the following table.
IT2
1
1
1
ADDRESS
IT1
DECODE
0
0
1
LOGIC
IT0
0
1
0
Channel control state machine
Data pipeline
Both
IEEE 1284-Compatible Parallel Interface — CD1283
Requestor
AD[6:0]
CS*
SVCACKP*
DGRANT*
R/W*
DS*
CD1283
DB[7:0]
CPU
DATA
31