SCD1283 INTEL [Intel Corporation], SCD1283 Datasheet - Page 4

• Manufacturer Part Number: SCD1283
• Description: IEEE 1284-Compatible Parallel Interface
• Manufacturer: INTEL [Intel Corporation]

CD1283 — IEEE 1284-Compatible Parallel Interface
6.0
7.0
4
5.7
5.8
5.9
5.10
Programming
6.1
6.2
6.3
Detailed Register Descriptions
7.1
7.2
7.3
7.4
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
Protocol Timing ................................................................................................... 41
General-Purpose I/O Port ................................................................................... 42
Parallel Port Interface.......................................................................................... 42
Hardware Configurations .................................................................................... 44
5.10.1 Interfacing to an Intel‚ Microprocessor-Based System ........................... 45
5.10.2 Interfacing to a Motorola‚ Microprocessor-Based System...................... 46
Overview ............................................................................................................. 47
Initialization ......................................................................................................... 47
6.2.1
6.2.2
ASCII Code Tables ............................................................................................. 51
Global Registers.................................................................................................. 53
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
Virtual Registers.................................................................................................. 56
7.2.1
7.2.2
Parallel Pipeline Registers .................................................................................. 57
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
7.3.10 Parallel FIFO Fill Pointer Register.......................................................... 63
7.3.11 Parallel FIFO Holding Registers............................................................. 63
7.3.12 Parallel FIFO Quantity Register ............................................................. 64
7.3.13 Parallel FIFO Status Register................................................................. 64
7.3.14 Parallel FIFO Threshold Register........................................................... 65
7.3.15 Run-Length Count Register ................................................................... 66
7.3.16 Stale Data Timer Count Register ........................................................... 66
7.3.17 Stale Data Timer Period Register........................................................... 67
Parallel Port Registers ........................................................................................ 67
Compatibility Mode................................................................................. 40
Reverse-Nibble and Reverse-Byte Modes ............................................. 40
ID Request ............................................................................................. 41
ECP Mode.............................................................................................. 41
EPP Mode .............................................................................................. 41
Device Reset.......................................................................................... 47
Service Acknowledge Handling.............................................................. 49
Access Enable Register ......................................................................... 53
Global Firmware Revision Code Register .............................................. 53
General-Purpose I/O Direction Register................................................. 54
General-Purpose I/O Register................................................................ 54
Parallel Interrupt Register ...................................................................... 54
Prescaler Period Register ...................................................................... 55
Service Request Register ...................................................................... 55
End-of-Service Request Register........................................................... 56
Parallel Interrupt Vector Register ........................................................... 56
Data Error Register ................................................................................ 57
DMA Buffer Data Register...................................................................... 58
Holding Register Status Register ........................................................... 58
Host Timeout Value Register ................................................................. 59
Local Interrupt Vector Register .............................................................. 60
Parallel Auxiliary Control Register.......................................................... 61
Parallel Channel Reset Register ............................................................ 61
Parallel FIFO Control Register ............................................................... 62
Parallel FIFO Empty Pointer Register .................................................... 63
............................................................................................................. 47
........................................................................... 53
Datasheet