SCD1283 INTEL [Intel Corporation], SCD1283 Datasheet - Page 51

• Manufacturer Part Number: SCD1283
• Description: IEEE 1284-Compatible Parallel Interface
• Manufacturer: INTEL [Intel Corporation]

6.3
Datasheet
POLL DEVICE AGAIN
00
08
10
18
20
Figure 16. Polling Flow Chart
Table 8. Hexadecimal — Character (Sheet 1 of 2)
SERVICE DMA REQUEST
RETURN ID TO HOST
CHANGE DIRECTION
CAN
NUL
DLE
BS
SP
RESET PRINTER
ASCII Code Tables
01
09
19
21
11
SOH
DC1
EM
HT
!
DMAREQ
DirCh
0A
1A
02
12
22
SET
SERVICE NEGOTIATION
SUB
HARDWARE RESET
STX
DC2
SOFTWARE RESET
INITIALIZE DEVICE
NL
“
CHANGE
PCISR
SVRR
TEST
TEST
TEST
TEST
NSR
PIR
0B
1B
03
13
23
PPort SET
NegCh SET
SRP SET
DC3
ESC
ETX
VT
#
IEEE 1284-Compatible Parallel Interface — CD1283
SigCh
Pipeline SET
0C
1C
04
14
24
POLL DEVICE AGAIN
NOTE: It may not be necessary to poll the PFSR if
INTERRUPT
SERVICE
CHANGE
EOT
DC4
SIGNAL
NP
FS
TEST
$
SSR
DMA requests are enabled. With DMA
requests enabled, the DMAREQ bit
(SVRR[7]) can be polled to determine when a
FIFO threshold is exceeded. If DMA requests
are disabled, the PFSR register must be
polled to determine when to move data to and
from the FIFO. If DMA requests are enabled,
data must be read through the DMABUF
register; this requires a 16-bit data bus.
0D
1D
05
15
25
INTERRUPT
SERVICE
ERROR
PFSR
ENQ
TEST
PFSR
NAK
TEST
CR
GS
%
= 00H
DataErr
06
0E
16
1E
26
APPROPRIATE
REGISTER
HOLDING
SERVICE
HRSR
TEST
ACK
SYN
SO
RS
&
HR DATA
FF FULL
HR TAG
EMPTY
OR
OR
07
0F
17
1F
27
SVC.
FIFO
BEL
ETB
US
SI
‘
51