SCD1283 INTEL [Intel Corporation], SCD1283 Datasheet - Page 78

• Manufacturer Part Number: SCD1283
• Description: IEEE 1284-Compatible Parallel Interface
• Manufacturer: INTEL [Intel Corporation]

CD1283 — IEEE 1284-Compatible Parallel Interface
8.3
8.3.1
78
Timing
No.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Table 12. Asynchronous Timing Reference Parameters (Sheet 1 of 2)
t
t
t
t
t
t
t
t
t
10
12
13
14
15
16
17
18
19
20
21
22
23
24
11
1
2
3
4
5
6
7
8
9
Figure
17
19
19
19
19
19
19
19
19
19
19
20
20
18
18
18
21
21
22
22
24
19
22
22
24
AC Characteristics
Asynchronous Timing
Refer to
RESET*
Address setup time to CS* or DS*
R/W* setup time to CS* or DS*
Address hold time after CS*
R/W* hold time after CS*
DTACK* low to read data valid
DTACK* low from CS* or DS
Data bus tristate after CS* or DS* high
CS* or DGRANT* high from DTACK* low
DTACK* inactive from CS* or DGRANT* and DS* high
DS* high pulse width
Write data valid from CS* and DS* low
Write data hold time after DS* high
Clock period (T
Clock low time
Clock high time
Propagation delay, DGRANT* and DS* to DPASS*
Setup time, SVCACK* to DS* and DGRANT*
Setup time, DMAACK* to rising edge of CLK
Hold time, read data after rising edge of CLK
Setup time, write data to rising edge of CLK
DTACK* active pull-up time
Data valid after falling edge of CLK (DMA read)
Hold time, DMAREQ* after DMAACK* falling edge,
last DMA cycle
Figure 17
1
low pulse width
1
(@ V
CLK
1
through
)
1, 3
CC
= 5 V
Parameter
Figure 25
4
2
5%, T
for the reference numbers in
A
= 0 C to 70 C)
0.3 T
0.3 T
2 T
40.0
MIN
10
10
10
10
10
10
10
10
0
0
0
0
0
Table
0
CLK
CLK
CLK
12.
4 T
1 CLK
0.7 T
0.7 T
1T
CLK
MAX
1000
30
35
30
25
10
40
CLK
CLK
CLK
15
30
Datasheet
T
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK