SCD1283 INTEL [Intel Corporation], SCD1283 Datasheet - Page 66

• Manufacturer Part Number: SCD1283
• Description: IEEE 1284-Compatible Parallel Interface
• Manufacturer: INTEL [Intel Corporation]

CD1283 — IEEE 1284-Compatible Parallel Interface
7.3.15
7.3.16
66
Register Name: RLCR
Register Description: Run-Length Count
Access: R/W
Register Name: SDTCR
Register Description: Stale Data Timer Count
Access: R/W
Bit 7
Bit 7
0
Run-Length Count Register
This register works with PFHR1 and PFHR2 to perform run-length encoding/decoding when the
RLEen bit (PFCR[3]) is set (the parallel port must be in ECP mode; in other modes, run-length
encoding will not occur).
In the transmit direction, strings of three or more identical characters are recognized and
compressed. The running count of identical characters is kept in the RLCR. Once the sequence is
broken by a different character or the end of the transmit burst transfer, the count and a single copy
of the duplicated character are put in the FIFO.
In the receive direction, run-length codes can be received from the remote device. These codes are
recognized ‘on the fly’ as data flows from the FIFO through the Holding register pipeline. A run-
length code is diverted to the RLCR. The subsequent character from the FIFO is duplicated (held in
PFHR1) while the RLCR is decremented. Once the RLCR reaches zero, normal pipeline data
movement is resumed. If run-length codes are being received by the parallel port but RLEen is not
set, the codes will enter PFHR1 and PFHR2 as tagged data and cause interrupts to the host. The
host must directly read the tagged Holding register to remove the character from the pipeline and
clear the tag.
Stale Data Timer Count Register
This register determines the period used to signal stale data in the FIFO. The timer is used only in
the receive direction. Each time a new character is placed in the FIFO from the parallel port, the
SDTCR is reloaded from the SDTPR and down-counting begins at the tick rate. If the counter
reaches zero, the Stale bit (PFSR[2]) is set. If the amount of data available is greater than or equal
to one word, a DMA request is made to move all remaining whole words to the host by DMA
transfer. Once the DMA transfer is complete, a single remaining character causes an interrupt to the
host to remove the character by reading PFHR2.
This register is cleared by device or FIFO reset. Clearing it manually causes the Stale bit to be true.
Bit 6
Bit 6
Bit 5
Bit 5
8-Bit Stale Data Timer Count
Bit 4
Bit 4
7-Bit Unsigned Binary Count
Bit 3
Bit 3
Bit 2
Bit 2
Bit 1
Bit 1
8-Bit Hex Address: 3D
8-Bit Hex Address: 37
Default Value: 00
Default Value: 00
Datasheet
Bit 0
Bit 0