LC89075W-H SANYO [Sanyo Semicon Device], LC89075W-H Datasheet
LC89075W-H
Related parts for LC89075W-H
LC89075W-H Summary of contents
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... The LC89075W-H also incorporates a high performance 24-bit single-end input ΔΣ stereo analog to digital converter that supports sampling frequencies 96kHz, and an audio selector that can support 8-channel data. The LC89075W complete analog and digital front-end for use in various systems including AV receivers, digital TVs, and DVD recorders. ...
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... Package Dimensions unit : mm (typ) 3190A 12.0 10 0.5 0.18 (1.25) SANYO : SQFP64(10X10) LC89075W-H 2 S/left justified 4-line input ×6 and 4-line output ×2 6-line input ×1, 4-line input ×5 and 6-line output ×1 7-line input ×1, 4-line input ×4 and 7-line output ×1 0.15 No.A1858-2/69 ...
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... DGND 56 RXIN8 57 RXIN7 58 RXIN6 59 RXIN5 60 RXIN4 61 RXIN3 62 RXIN2 63 RXIN1 LC89075W-H LC89075W Figure 4.1 LC89075W-H Pin Assignment 32 XIN 31 XOUT 30 XMCK 29 MPIO4 28 MPIO3 27 MPIO2 26 MPIO1 25 NPCMF 24 MUTEB 23 ERRF 22 MPOUT4 21 MPOUT3 20 MPOUT2 19 MPOUT1 DGND Top view No ...
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... MPOUT3 O LR clock output pin DSD data output pin 7, 8ch/8ch audio data output pin LC89075W-H Table 5.1 Pin Functions Function : Master clock input pin : Master clock input pin : Bit clock input pin : Bit clock input pin : LR clock input pin ...
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... O Analog or digital data detection flag output pin Digital power supply (3.3V) 43 DGND Digital GND LC89075W-H Function : Master clock input pin : Bit clock input pin : LR clock input pin : DSD data input pin : 2ch audio data input pin : DSD data input pin from ADC, [DATAIN], [MPIN4], [MPIO4], [RXIN5] ...
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... Pins 26, 27, 28 and 29: power-off reverse bias control are supported only when “L” level input during power-off. * Pin 46: 3.3V can be supplied when not using the ADC. In this case, making the power-down setting is recommended. * Each and DV DD power supply must be turned on and off at the same timing to prevent latch-up. LC89075W-H Function : Master clock input pin ...
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... Group: C (input) DIR Error Data mute Non-PCM C bit info. Clock & data Group: A (input) Group: B (input) Group: C (input) || S/PDIF || S/PDIF || S/PDIF || S/PDIF Group: C (output) Figure 6.1 LC89075W-H Block Diagram ADC DIR 13 Group MUX Group: B (4×6):4 15 Group: C Group ADC 19 Group: A ...
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... ADINL, ADINR, RXIN1, RXIN2, RXIN3, RXIN4, RXIN5, RXIN6, RXIN7, and RXIN8 pins 7.2.5: MCKIN, BCKIN, LRCKIN, DATAIN, MPIN1, MPIN2, MPIN3, MPIN4, MPIN5, and MPIN6 pins XIN, MPIO1, MPIO2, MPIO3, MPIO4, XMODE, CSB, SCK, SI, RXIN1A, RXIN2A, and RXIN3A pins 7.2.6: MCKOUT pin 7.2.7: Output pins other than MCKOUT LC89075W-H Conditions 7.1.1 7.1.2 7.1.3 7 ...
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... A-weighted, except when “ADCOPR[1:0]=10” 7.3.7: fs=96kHz, A-weighted, except when “ADCOPR[1:0]=10” 7.3.8: fs=48kHz, -60dBFS, A-weighted 7.3.9: fs=96kHz, -60dBFS, A-weighted 7.3.10: Delay calculation for the digital filter 7.3.11: -3dB LC89075W-H Conditions min 7.3.1 8 2.048 7.3.2 7.3.3 -4 ...
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... XIN=24.576MHz, fs=6kHz/ADC, when Figure 9.6 setting ADINL=ADINR=No signal 7.5.6: Analog and digital audio data detection setting standby current, “ADCOPR[1:0]=10”, “SDMODE=1”, “DSTASEL=1”, XIN=24.576MHz, fs=6kHz/ADC, when Figure 9.6 setting, however “DIROPR=0”, “RXDSEL[3:0]=0000” ADINL=ADINR=No signal, S/PDIF dose not input LC89075W-H Conditions min 7.4.1 0 7.4.2 2 ...
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... RXIN1 to 8 Input RXIN1A to 3A MPIO[4:1] MCKOUT Output MPOUT1 BCKOUT Output MPOUT2 LRCKOUT Output MPOUT3 DATAOUT Output MPOUT[3:1] LC89075W-H Symbol Conditions f RFS t RXDUY f XF 7.6.1 7.6.2 f XDUY f MCK1 f MCKDUY T j 7.6.3 f MCK2 f BCK1 f LRCK1 t MBO t BLO 7 ...
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... MCKIN, MPIN1 MPIO1, RXIN8 BCKIN, MPIN2 MPIO2, RXIN7 LRCKIN, MPIN3 MPIO3, RXIN6 DATAIN, MPIN4, MPIO4 RXIN5, MPIN1, MPIN2 MPIN3, MPIN5, MPIN6 MCKOUT MPOUT1 BCKOUT MPOUT2 LRCKOUT MPOUT3 DATAOUT MPOUT4 MPOUT[3:1] LC89075W-H Symbol Conditions f MCKIN1 7.7.1 f BCKIN 7.7.2 f LRCKIN 7.7.3 t IDLY 7.7.4 t BDSH 7.7.5 t MMO 7.7.6 t BBO 7.7.7 t LLO 7 ...
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... XMODE must be fixed to “H” before power is turned on in order to use the power-on reset function. 7.8.3: SI has to set to “L” input when turning the power on. t PORSL DV DD XMODE CSB t CSBtoSCK SCK t SIsetup SI Hi-Z SO Figure 7.3 SPI Microcontroller Interface AC Characteristics LC89075W-H Symbol Conditions min t PORSL 7.8.1 t RSTdw 7.8.2 200 f SCK t SCKdw 40 t SCKuw ...
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... System Settings (Common to ADC, DIR, and Audio selector) 8.1 Oscillation Amplifier Pin Settings (XIN, XOUT, XMCK) • The LC89075W-H features a built-in oscillation amplifier. Connect a quartz resonator, feedback resistor, and load capacitance to XIN and XOUT to configure an oscillation circuit. The figure below shows the connection diagram. ...
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... System Reset (XMODE) • The LC89075W-H features a built-in power-on reset circuit, and constantly monitors the power supply status. • When XMODE is set to “H” and the power is turned on, the system is reset by this power-on reset circuit. • When not using the power-on reset circuit, always set XMODE to “L” to reset the system during power-on. The system operates correctly when XMODE is set to “ ...
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... Connect to DGND (Pin No. 43) • The MPIO[4:1] pins can be set to input or output. In the initial status, these pins are set to output of Hi-Z. When not using these pins, use the initial setting and leave the pins open. LC89075W Data is output synchronized with the BCKOUT falling edge. ...
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... Current consumption can be further reduced by simultaneously setting to stop the DIR function and fix the output clock pin outputs to suppress current consumption other than the ADC. See below for further details, “9.6 Analog Audio Data Detection”. LC89075W-H Table 9.1 ADC Operation Mode Comparison When PLL is unlocked: Operating When PLL is locked: Reset (ADC also resets when ERRF is “ ...
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... When not using the built-in ADC, 3.3V can be supplied to the AV DD pin that normally requires a 5V supply. • The ADC can operate even when 3.3V is supplied, but the characteristics are not guaranteed. Therefore recommended to set the power-down mode when not using the ADC. LC89075W-H Set “ ADCOPR[1:0]=00 ” ...
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... MPIO[3:1]. The system doesn't operate normally when there is no clock input to MPIO[3:1]. Therefore, must be supply the clock to MPIO[3:1] in slave mode. • The data that has been analog to digital converted according to the DAFORM register setting is output from MPIO4 and MPOUT4. These output data are not affected by MUTEB. LC89075W-H ADC Output Pin Clock Frequency (Hz) Sampling ...
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... The HPF cutoff frequency is 1.85Hz when fs=48kHz. The frequency response is proportional to fs. 9.4 PGA • The LC89075W-H incorporates an analog PGA (Programmable Gain Amplifier). • The PGA can be set to -4.5dB to +6dB in 1.5dB steps with the ADPGA[2:0] register. • The input impedance is 27kΩ, and the ADC full-scale input is proportional to the AV DD voltage =0.6×AV DD ...
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... Soft Mute/Attenuator • The LC89075W-H incorporates a digital volume that can adjust from 0dB to -63.5dB and -∞dB. • The digital volume is set with the ADVOL[7:0] register. When the ADVOL[7:0] register setting is changed, the volume changes according to the ADFDSP[2:0] register setting. The volume changes the gain in 0.25dB steps. ...
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... Analog Audio Data Detection (DSTATE) • The LC89075W-H can detect the existence (‘Sound’ or ‘Silence’) of analog audio data. ‘Sound’ has the audio data above threshold level. ‘Silence’ has the audio data below threshold level. • The ‘Sound’ detection can be performed in normal operation mode or low sampling rate operation mode. ...
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... ADC State Operation MUTEB DATAOUT ADC output Flag DSTATE (Analog data detection flag) Figure 9.5 ADC Reset Processing Timing (When “ADBMOD=0”) LC89075W-H SDMODE=0 (‘Silence’ detection) Lock Reset DIR output fs=48kHz: 341ms 16384/f fs=96kHz: 170ms “ADBMOD=0” SDMODE=1 (‘Sound’ detection) ...
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... PLL output PLL output 256fs 512fs LC89075W-H *: When the RXFSLIM[1:0] register that limits the input S/PDIF reception frequency is set and data that exceeds this setting is judged, the same processing is executed as when the PLL is unlocked, and subsequent processing is not performed ...
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... In addition, when the oscillation amplifier is automatically stopped, the XMCK clock is not output. • When “SW1SEL[2:0]=001”, “SW2SEL[2:0]=001” or slave mode “MPSEL[1:0] =10 or 11”, the oscillation amplifier is set to continuous operation mode. This has higher priority than the AMPOPR[1:0] register setting. LC89075W-H PLL Output (MHz) “RXCKAT=0” ...
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... The clocks output from the DIR block are input to the output selector and output to MCKOUT, BCKOUT and LRCKOUT. DIR Output The characters in parenthesis are output pins. Master clock (MCKOUT) Bit clock (BCKOUT) L/R clock (LRCKOUT) LC89075W-H Input fs 1/1 Autom atic 1/2 1/4 “R XCKAT” 512fs M anual 256fs 128fs “ ...
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... ERRF MCKOUT RXIN** Digital data PLL locked status XIN clock PLL clock MUTEB (DIRMUTP=0) ERRF MCKOUT LC89075W-H Digital data UNLOCK After PLL lock XIN clock (a) Lock-in stage LOCK Same timing as ERRF PLL clock (b) Unlock stage Figure 10.3 Clock Switching Timing LOCK 3ms to 144ms 2 ...
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... PLL status ERRF MCKOUT PLL clock BCKOUT LRCKOUT (c) When set to “RXLIM[1:0]=10” (Receive frequency is limited to 48kHz or lower) Figure 10.4 Output Clocks Generated When Input Data Reception Is Limited LC89075W-H Fs=192kHz LOCK PLL clock (a) When set to “RXLIM[1:0]=00” (No limit on inputs) Fs=192kHz LOCK XIN clock ...
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... The RXTHR1[3:0] and RXTHR2[3:0] registers are initially set so that RXOUT and MPOUT4 output “L.” When not using RXOUT and MPOUT4, muting these pins is recommended. Optical 0.01μF to 0.1μF Coaxial 50Ω LC89075W-H Input Data Reception Range LC89075W 100Ω RXIN[8:1] RXIN[3:1]A Setting examples: “RX1ASEL=1” “RX2ASEL=1” “RX3ASEL=1” ...
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... PLL locked status MUTEB DIRMUTP=0 ERRF DATAOUT PLL locked status MUTEB DIRMUTP=0 ERRF DATAOUT Demodulation data Figure 10.6 Timing Chart of DATAOUT Output Data Switching LC89075W-H UNLOCK LOCK ADC data Muted (a) Lock-in stage LOCK UNLOCK Muted (b) Unlock stage Demodulation data ADC data No.A1858-30/69 ...
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... The non-PCM data is the information that is output from NPCMF and subject to the NPSEL register setting. • The PLL is set to the unlock state when the ADC clock and the data output have been selected by “SW1SEL[2:0]=001” and ERRF outputs the error flag. LC89075W-H No.A1858-31/69 ...
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... When preambles B, M, and W are detected, the PLL becomes locked and data demodulation begins. • The demodulation data is output from the LRCKOUT edge after ERRF turns to "L." ERRF Lock Signal LRCKOUT DATAOUT Figure 10.8 Data Processing When Data Demodulation Starts LC89075W-H Input Parity Error (a) “L” “L” Output “L” “L” ...
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... The calculation results can be readout with the microcontroller interface. (RXFSC[3:0] register readout) • The input data sampling frequency calculation value and channel status fs information are compared and if the sampling frequency is a same deal, “1” is read from the RXFSFLG register. LC89075W-H Table 10.6 NPCMF Output Output Conditions PCM audio data (bit 1 = “ ...
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... Description of Input/Output Audio Selector • The LC89075W-H incorporates a peripheral circuit audio selector. • The audio selector can select the following configurations. 1) 2-channel data support 2) 6-channel data and 2-channel data support 3) 8-channel data and 2-channel data support 11.1 2-channel Data Support (Input pins: MCKIN, BCKIN, LRCKIN, DATAIN, MPIN[4:1], MPIO[4:1], RXIN[8:5]) (Output pins: MCKOUT, BCKOUT, LRCKOUT, DATAOUT, MPOUT[4:1], MUTEB, NPCMF) • ...
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... RXIN6 (58) RXIN5 (59) 110 - 111 (Mute output) • The format of the audio data input to DATAIN, MPIN4, MPIO4 and RXIN5 should match the ADC and DIR output data format (DAFORM register setting). LC89075W-H Selector Input Selector Output → MCKOUT (13) → BCKOUT (14) → LRCKOUT (15) → ...
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... The DIR demodulated data and clocks are not output from MPOUT[4:1]. Table 11.3 External Flag Input/Output Configuration in 2-channel Data Selector Setting FLGOUT Register 1 MPIN5 (11) MPIN6 (12) LC89075W-H Selector Input Selector Output MPOUT1 (19) MPOUT2 (20) MPOUT3 (21) → MPOUT4 (22) → ...
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... Table 11.4 Clock and Data Input/Output Configuration in 6-channel Data Selector Setting (MCKOUT, BCKOUT, LRCKOUT, DATAOUT and MPOUT[4:1] output pins) SW1SEL SW2SEL Register Register 011 110 MPIN1 (7) MPIN2 (8) MPIN3 (9) MPIN4 (10) MPIN5 (11) MPIN6 (12) - S/PDIF input LC89075W-H “SW1SEL[2:0]” 4 “SW2SEL[2:0]” 4 “MCKOUTP” “D6CHMUT” Selector Input Selector Output → MCKOUT (13) → ...
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... RXIN6 (58) RXIN5 (59) 110 - 111 (Mute output) • The format of the audio data input to DATAIN, MPIO4 and RXIN5 should match the ADC and DIR output data format (DAFORM register setting). LC89075W-H Selector Input Selector Output → MCKOUT (13) → BCKOUT (14) → LRCKOUT (15) → ...
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... Figure 11.3 8-channel Data and 2-channel Data Support Audio Selector Configuration (Clock & Data MUX: 7-bits×1 input, 4-bits×4 inputs, 7-bits×1 output) • In the 8-channel data selector configuration, the MPOUT4 output is subject to the RXTHR2 register setting. LC89075W-H “SW1SEL[2:0]” 4 “SW2SEL[2:0]” ...
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... Table 11.8 External Flag Input/Output Configuration in 8-channel Data Selector Setting FLGERR FLGOUT Register Register × 1 MPIN4 (10) × 1 MPIN5 (11) MPIN6 (12) LC89075W-H Selector Input Selector Output → MCKOUT (13) → BCKOUT (14) → LRCKOUT (15) → DATAOUT (16) → MPOUT1 (19) → MPOUT2 (20) → MPOUT3 (21) → ...
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... MUTEB. 12. Digital Audio Data Detection • In addition to analog audio data detection, the LC89075W-H can also detect the existence of digital audio data (2- channel data only) that are output from DATAOUT set by DSTASEL register. (“DSTASEL=1”) • The DATAOUT audio data detection process differs for PCM data and non-PCM data. The data is delimited by the channel status bit 1 information, the DTS-CD non-PCM detection flag, and also the MPIN6 input signal when “ ...
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... Data read is performed by R/W=1 and the data is output from SO after the register address is set. • SO outputs high impedance when R/W=0 or when CSB is “H”. • The LC89075W-H incorporates an address counter, and is controlled in the current address access mode that performs read/write while automatically incrementing the address the random address access mode that reads/writes the data for an arbitrary address ...
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... SI R Hi-Z Figure 14.4 Random Address Access Mode Input Timing Diagram CSB SCK SI R Hi-Z Figure 14.5 Random Address Access Mode Output Timing Diagram LC89075W-H MSB LSB MSB LSB ...
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... SCK SI Hi-Z SO Figure 14.6 INTB Output Timing Example (when “INTBP=0”) LC89075W-H Table 14.1 Interrupt Source Setting Contents Output when ERRF pin status has changed. Output when input fs calculation result has changed. Output when channel status data of the first 40 bits has been updated. ...
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... RXCS15 R 13h RXCS23 R 14h RXCS31 R 15h RXCS39 R 16h RXPC7 R 17h RXPC15 • “0” reserved bit. Always must be set to “0”. LC89075W-H Table 14.2 Register Map DIROPR ADCOPR1 ADCOPR0 AMPOPR1 INTBP MCKOUTP DSTATEP RX3ASEL RX2ASEL RX1ASEL PI2 PI1 PI0 ...
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... The ADC low sampling rate operation mode performs analog to digital conversion at 6kHz, and is set during analog audio data ‘Sound’ detection. The condition (required) for this mode is that “ADCOPR[1:0]=10” and “SDMODE=1” are set. • When “DIROPR=1” is set while the PLL is locked, this setting is executed after the clock source is switched to XIN. LC89075W ...
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... MPOUT[4:1] output (SW2SEL[2:0] register setting). • Note that the detector circuit doesn't operate when the clock that is set “DSTASEL=1” and is selected by SW1SEL 2:0 register is not output from MCKOUT, BCKOUT, and LRCKOUT pins. Therefore, the DSTATE is not changed from the result before. LC89075W ...
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... RXIN3A input function setting 0: TTL input level supported input (initial value) 1: Coaxial input level compatible input NPSEL NPCMF pin output contents setting 0: Output only channel status, bit 1 (initial value). 1: Output channel status, bit 1, IEC61937, and DTS-CD detection flag. LC89075W RX2ASEL RX1ASEL 0 0 ...
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... Switching to the MPIO[4:1] input setting (“MPSEL[1:0]=01”) must be performed from the MPIO[4:1] high impedance output status. • MPSTA[1:0] can be set only when “MPSEL[1:0]=00” is set. LC89075W-H Address: 03h; System Setting (I/O Pin Setting ...
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... Adjust the MPIN4, MPIN5 and MPIN6 input signals with the MPIN4P, MPIN5P and MPIN6P registers so that the signals output from ERRF, MUTEB and NPCMF match the DIRERRP, DIRMUTP and DIRPCMP register conditions. • Non-PCM data is data detected according to the NPSEL register setting. LC89075W ...
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... LRCKOUT output. Note that the MUXMOD register must not be used when LR clock select the source without the LRCKOUT clock output or when DSD data is input, there clock input, to avoid the possibility of errors in operation. • OUTMUT register is set, when the ‘Sound’ detection of analog or digital audio data is executed with low current consumption. LC89075W MUXMOD ...
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... DATAOUT: MPIO4 pin input 2ch supported audio data output 101: RXIN[8:5] pin input signal output MCKOUT: RXIN8 pin input master clock output BCKOUT: RXIN7 pin input bit clock output LRCKOUT: RXIN6 pin input channel clock output DATAOUT: RXIN5 pin input 2ch supported audio data output LC89075W SW2SEL1 SW2SEL0 0 ...
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... RXIN[8:5] pin input signal output MPOUT1: RXIN8 pin input master clock output MPOUT2: RXIN7 pin input bit clock output MPOUT3: RXIN6 pin input channel clock output MPOUT4: RXIN5 pin input 2ch supported audio data output LC89075W-H Continued on next page. No.A1858-53/69 ...
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... When the output buffer function of the clock and data are stopped and current consumption is decreased, the OUTMUT register is set. Note that ‘Sound’ detection dose not function when the output function of the clock and data are stopped with “SW1SEL[2:0]=110 or 111” (“L” output). LC89075W-H No.A1858-54/69 ...
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... NLEVEL[3:0] registers. • When performing detection on analog data, the judgment level variations can be increased by also using the ADPGA[2:0] register that sets the PGA. However, care should be taken for the ADPGA[2:0] register setting affects the normal ADC operation. LC89075W NLEVEL1 ...
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... The transition time is calculated from the following formula. Other than when “ADFDSP[2:0]=000” or “ADVOL[7:0]=FFh” is set. Transition time from the ADVOL[7:0] register setting value to -∞ = (256-ADVOL[7:0]) × ADFDSP[2:0] = (256-(0, 0.25, 0.5, 0.75 ... 63.5dB/0.25dB) × (1/fs, 2/fs, 4/fs, 8/fs, 16/fs) LC89075W-H Address: 08h; ADC Data Control Setting ...
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... LC89075W-H Address: 09h; ADC Output Attenuator Setting D5 D4 ADVOL5 ADVOL4 ADVOL3 0 0 R/W R/W 0dB, 0010_1000: -10.00dB, 0010_1001: -10 ...
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... LC89075W-H 1010_1000: -42.00dB, 1101_1000: 1010_1001: -42.25dB, 1101_1001: 1010_1010: -42.50dB, 1101_1010: 1010_1011: -42.75dB, 1101_1011: 1010_1100: -43 ...
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... When input fs calculation cannot be done by “RXCKAT=0”, the PLL clock is set to 256fs output. • Set the RXCKAT,RXCKDEV[1:0] and RXMCK[1:0] register while the PLL is unlocked. This setting is executed after the PLL is locked. However, after PLL is locked, RXMCK[1:0] register can change by RXCKMU register. LC89075W-H Address: 0Ah; DIR Clock Setting D5 ...
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... RXIN4 0100: RXIN5 0101: RXIN6 0110: RXIN7 0111: RXIN8 1000: RXIN1A 1001: RXIN2A 1010: RXIN3A 1011: MPIO1 1100: MPIO2 1101: MPIO3 1110: MPIO4 1111: Connected to GND. • The MPIO[4:1] data input is used by “MPSEL[1:0]=01”. LC89075W RXDSEL1 RXDSEL0 RXTHR13 R/W R/W R/W D2 ...
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... MPIO1 1100: MPIO2 1101: MPIO3 1110: MPIO4 1111: Fixed at “L” (initial value). • The RXTHR2[3:0] register setting contents are output from MPOUT4, but the MPOUT4 setting conforms to the SW2SEL[2:0] register. LC89075W-H Address: 0Ch; DIR Through Data Setting ...
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... The RXERWT[1:0] register setting defines the time after the PLL is locked until ERRF outputs “L” to cancel the error. The demodulated audio data is output after the ERRF error is canceled, so when problems occur such as the start of the data being cut off, change this setting. LC89075W-H Address: 0Dh; DIR System Setting D5 ...
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... When the data match, the data is considered to have been updated and the update flag is output. • Likewise, the burst preamble Pc update flag process compares the 16 bits of data of the previous block with the current data. When the data match, the update flag is output. LC89075W-H Address: 0Eh; DIR Interrupt Source Setting D5 ...
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... The ERRF, NPCMF and DSTATE pin statuses can be read from the OERROR, OUNPCM and ODATAM registers, regardless of the INTB output setting. • The channel status information can be read from the OEMPF register, regardless of the INTB output setting. LC89075W-H Address: 0Fh; DIR Interrupt Source Readout D5 ...
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... The RXFSFLG register compares the calculated sampling frequency value of the input data with the fs information of the channel status, and is output when the sampling frequency results match. • When the DTS-CD(ES) sync signal of the RXDTSES register is detected, the DTS-CD sync signal of the RXDTS51 register is also detected at the same time. LC89075W ...
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... RXCS13 bit13 RXCS14 bit14 RXCS15 bit15 13h RXCS16 bit16 Source number RXCS17 bit17 RXCS18 bit18 RXCS19 bit19 • For details, check the IEC60958 Specifications. LC89075W RXCS5 RXCS4 RXCS3 RXCS13 RXCS12 RXCS11 RXCS21 RXCS20 RXCS19 RXCS29 RXCS28 RXCS27 RXCS37 RXCS36 ...
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... For the latest information, check the specifications issued from each license. LC89075W RXPC5 RXPC4 RXPC3 RXPC13 RXPC12 RXPC11 Table 14.4 Burst Preamble Pc Read Registers Pc Bit bit0 Data type bit1 bit2 bit3 bit4 bit5 ...
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... F to 0.01 μ 100 Ω R4 100 Ω R5 0.068 μ 0.001 μ LC89075W-H 5V 3.3V M-computer LC89075W-H 56 SQFP-64 (12×12 HDMI Application ...
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... SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of October, 2011. Specifications and information herein are subject to change without notice. LC89075W-H PS No.A1858-69/69 ...