LC89075W-H SANYO [Sanyo Semicon Device], LC89075W-H Datasheet - Page 41

no-image

LC89075W-H

Manufacturer Part Number
LC89075W-H
Description
Digital Audio Interface Receiver with Stereo ADC and Audio Selector
Manufacturer
SANYO [Sanyo Semicon Device]
Datasheet
• The initial status of each ERRF, MUTEB and NPCMF output is shown below.
• When the polarities differ from the externally supplied signals, the polarities can be changed with the MPIN4P,
• The format of the audio data input to DATAIN, MPIN[3:1], MPIN[6:4] and MPIO4 is subject to the DAFORM
11.4 Clock and Data Switching and Mute Process
• Selector switching with the SW1SEL[2:0] and SW2SEL[2:0] registers is normally processed immediately after these
• Output data mute is set with the DATAMUT, D6CHMUT and D8CHMUT registers. When these mute-setting
• MUTEB is output according to changing DIR and ADC blocks. Therefore, when the selector is used, MUTEB is
12. Digital Audio Data Detection
• In addition to analog audio data detection, the LC89075W-H can also detect the existence of digital audio data (2-
• The DATAOUT audio data detection process differs for PCM data and non-PCM data. The data is delimited by the
• The ‘Sound’ or ‘Silence’ detection for PCM data is the same as that for analog audio data. The judgment levels are set
• The ‘Sound’ or ‘Silence’ detection for non-PCM data is judged by whether the mute status (0 data) is established. The
• The DSTATE output is delayed by 1/2 frame relative to the DATAOUT output data. Moreover, the audio data
• The digital audio data detection does not support DSD data. Note that when “DSTASEL=1” is set and DSD data is
13. Microcontroller Register Output (Expanded Output)
• The serial data input from the microcontroller interface is converted to parallel data and output from MPIO[4:1] pins.
• Set the data to be output to MPIO[4:1] pins in the PI[3:0] register (address 03h).
• The data written to the PI[3:0] register is output to MPIO[4:1] pins.
MPIN5P and MPIN6P registers or the DIRERRP, DIRMUTP and DIRPCMP registers.
register setting. The initial value is I
registers are set, but this switching can be synchronized to LRCKOUT with the MUXMOD register. However, note
that in this case the switching process cannot be performed when LRCKOUT is not output. In addition, the LR clock
is not input in systems that handle DSD data, so the MUXMOD register must not be used with these systems.
registers are set, MUTEB is muted with the MUTREF register. However, at the initial setting, the DATAMUT,
D6CHMUT and D8CHMUT register settings are not reflected. However, mute processing cannot be performed for
both DSD channels.
changed according to the state of DIR and ADC. To process the mute with MUTEB when the selector is used, the
signal output to MUTEB is changed to MPIN5. However, when MPIN[6:1] is used for clock and 6ch data input, the
mute signal cannot be output from MUTEB.
channel data only) that are output from DATAOUT. It is set by DSTASEL register. (“DSTASEL=1”)
channel status bit 1 information, the DTS-CD non-PCM detection flag, and also the MPIN6 input signal when
“FLGOUT=1” is set. The ‘Sound’ or ‘Silence’ detection can be selected with the SDMODE register.
with the YLEVEL[3:0] and NLEVEL[3:0] registers. The output data format conforms to the UDFORM register. The
detection results are output from the DSTATE pin and the ODATAM register.
‘Silence’ is detected when all 24-bit of channel data are 0 data, and the ‘Sound’ is detected in all other cases. When
performing detection for non-PCM data, the YLEVEL[3:0] and NLEVEL[3:0] register settings are not reflected.
detection doesn't operate when the output clock selected with SW1SEL[2:0] register has stopped. At this time,
DSTATE is continuously output the result before and becomes wrong information. Therefore, do not select the source
without the clock supply.
output, DSTATE outputs incorrect results.
This function operates when “MPSEL[1:0]=00” and “MPSTA[1:0]=11” are set.
Output
“H”
“L”
Table 11.11 Initial Setting Status of the ERRF, MUTEB, and NPCMF Output Pins
PLL lock error cancelled
PLL unlock state
“ DIRERRP=0 ”
ERRF Pin
2
S output format.
LC89075W-H
Output data mute processing
“ DIRMUTP=0 ”
MUTEB Pin
Data output
Non-PCM data output
PCM data output
“ DIRPCMP=0 ”
NPCMF Pin
No.A1858-41/69

Related parts for LC89075W-H