LC89075W-H SANYO [Sanyo Semicon Device], LC89075W-H Datasheet - Page 54

• Manufacturer Part Number: LC89075W-H
• Description: Digital Audio Interface Receiver with Stereo ADC and Audio Selector
• Manufacturer: SANYO [Sanyo Semicon Device]

Continued from preceding page.
• The SW1SEL[2:0], FLGERR, SW2SEL[2:0] and FLGOUT register settings are processed according to the
• The change of MPIO[4:1] pins to the input terminal is set to “MPSEL[1:0]=01”.
• When “SW1SEL[2:0]=001” is set, the DIR is unlocked regardless of whether there is digital data, and the error flag is
• The setting and the release of “SW2SEL[2:0]=001” are executed via the reset processing of ADC.
• 6-channel data and 8-channel data processing are set as follows.
• In order to switch the ERRF, MUTEB and NPCMF outputs to the MPIN4, MPIN5 and MPIN6 input signals when
• When “DSTATE=1”, the ‘Sound’ or ‘Silence’ detection is executed for the output data selected with SW1SEL[2:0]
MUXMOD register. When “MUXMOD=1”, the SW1SEL[2:0], FLGERR, SW2SEL[2:0] and FLGOUT register
settings must be made in the LR clock constantly supplied status. When LR clock supply is stopped, these register
settings are not executed.
output from ERRF. When switched from the PLL locked status, the ADC data is output after mute processing
(MUTEB pulse output period).
When the ADC data is output from DATAOUT by “SW1SEL[2:0]=000” or “SW1SEL[2:0]=001”, MUTEB is
changed by “SW2SEL[2:0]=001”. And, DATAOUT is muted while ADC is being reset. “SW2SEL[2:0]=001” is
recommended to be set or release after DATAOUT output data is muted. When the demodulation data of DIR is
output from DATAOUT by “SW1SEL[2:0]=000”, setting or release of “SW2SEL[2:0]=001” dose not influence
DATAOUT because the reset processing of ADC is not reflected in MUTEB at this time. When the slave of ADC is
set, these are similar.
switching to 8-channel data, also change the FLGERR and FLGOUT register settings at the same time as the
SW1SEL[2:0] and SW2SEL[2:0] settings.
register. When the output buffer function of the clock and data are stopped and current consumption is decreased, the
OUTMUT register is set. Note that ‘Sound’ detection dose not function when the output function of the clock and data
are stopped with “SW1SEL[2:0]=110 or 111” (“L” output).
SW2SEL[2:0]
FLGOUT
6-channel data processing: “SW1SEL[2:0]=011” and “SW2SEL[2:0]=110”
8-channel data processing: “SW1SEL[2:0]=010” and “SW2SEL[2:0]=111”
MUTEB and NPCMF output setting
110: MPIN[6:5] pin input signal output (6ch data supported)
111: MPIN[3:1] pin input signal output (8ch data supported)
0: MUTEB: Mute signal generated by the DIR (initial value).
1: MUTEB: MPIN5 pin input signal is output (polarity is inverted by MPIN5P register).
NPCMF: Non-PCM information generated by the DIR (initial value).
NPCMF: MPIN6 pin input signal is output (polarity is inverted by MPIN6P register).
MPOUT1: MPIN5 pin input 6ch supported audio data output
MPOUT2: MPIN6 pin input 6ch supported audio data output
MPOUT3: “L” output
MPOUT4: S/PDIF output (initial value is “L”, subject to RXTHR2[3:0] register)
MPOUT1: MPIN1 pin input 8ch supported audio data output
MPOUT2: MPIN2 pin input 8ch supported audio data output
MPOUT3: MPIN3 pin input 8ch supported audio data output
MPOUT4: S/PDIF output (initial value is “L”, subject to RXTHR2[3:0] register)
LC89075W-H
No.A1858-54/69