LC89075W-H SANYO [Sanyo Semicon Device], LC89075W-H Datasheet - Page 37

• Manufacturer Part Number: LC89075W-H
• Description: Digital Audio Interface Receiver with Stereo ADC and Audio Selector
• Manufacturer: SANYO [Sanyo Semicon Device]

11.2 6-channel Data and 2-channel Data Support
• This selector configuration can process one system of 6-channel data and five systems of 2-channel data.
• The selector output is set with the MUXMOD, SW1SEL[2:0] and SW2SEL[2:0] registers.
• The 2-channel data is output from DATAOUT. This output can be muted with the DATAMUT register.
• The 6-channel data is output from DATAOUT and MPOUT[2:1]. This output can be muted with the D6CHMUT
• The S/PDIF signal can be output from MPOUT4. This is set with the RXTHR2[3:0] register.
• DSD data I/O is also possible. However, mute processing cannot be performed for both DSD channels.
011
register.
SW1SEL
Register
LRCKIN
DATAIN
MCKIN
MPIO1 26
MPIO2 27
MPIO3 28
MPIO4 29
BCKIN
MPIN1
MPIN2
MPIN3
MPIN4 10
MPIN5 11
MPIN6 12
RXIN8 56
RXIN7 57
RXIN6 58
RXIN5 59
(Input pins: MCKIN, BCKIN, LRCKIN, DATAIN, MPIN[6:1], MPIO[4:1], RXIN[8:5])
(Output pins: MCKOUT, BCKOUT, LRCKOUT, DATAOUT, MPOUT[2:1])
ADC
PLL
X’tal
DIR
3
4
5
6
7
8
9
Table 11.4 Clock and Data Input/Output Configuration in 6-channel Data Selector Setting
110
Figure 11.2 6-channel Data and 2-channel Data Support Audio Selector Configuration
Master clock
Bit clock
LR clock
2ch data
Master clock
Bit clock
LR clock
2ch data
Master clock
Bit clock
LR clock || DSD
2ch data || DSD
Master clock
Bit clock
LR clock
1,2/6ch data
3,4/6ch data
5,6/6ch data
Master clock
Bit clock
LR clock || DSD
2ch data || DSD
Master clock
Bit clock
LR clock || DSD
2ch data || DSD
SW2SEL
Register
(MCKOUT, BCKOUT, LRCKOUT, DATAOUT and MPOUT[4:1] output pins)
(Clock & Data MUX: 6-bits×1 input, 4-bits×5 inputs, 6-bits×1 output)
MPIN1 (7)
MPIN2 (8)
MPIN3 (9)
MPIN4 (10)
MPIN5 (11)
MPIN6 (12)
-
S/PDIF input
“MPSEL[1:0]”
Selector Input
4
4
4
6
4
4
→
→
→
→
→
→
→
LC89075W-H
MCKOUT (13)
BCKOUT (14)
LRCKOUT (15)
DATAOUT (16)
MPOUT1 (19)
MPOUT2 (20)
MPOUT3 (21)
MPOUT4 (22)
Selector Output
“SW1SEL[2:0]”
“SW2SEL[2:0]”
“D6CHMUT”
“MCKOUTP”
“MPO4MUT”
1,2/6ch data || DSD
LR clock || DSD
Master clock input/output
Bit clock input/output
LR clock input/output
1, 2/6ch data input/output
3, 4/6ch data input/output
5, 6/6ch data input/output
"L" output
Input S/PDIF select output
“MUXMOD”
Master clock
3,4/6ch data
5,6/6ch data
S/PDIF
Bit clock
I/O Contents
13
14
15
16
19
20
21
22
MCKOUT
BCKOUT
LRCKOUT
DATAOUT
MPOUT1
MPOUT2
MPOUT3
MPOUT4
No.A1858-37/69