MAX11339ATJ+ Maxim Integrated, MAX11339ATJ+ Datasheet - Page 12

• Manufacturer Part Number: MAX11339ATJ+
• Description: Analog to Digital Converters - ADC 10-Bit 8Ch 500ksps SAR ADC
• Manufacturer: Maxim Integrated

Specifications of MAX11339ATJ+

• Rohs: yes
• Number Of Channels: 8
• Architecture: SAR
• Conversion Rate: 500 kSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Differential
• Snr: 61.5 dB
• Interface Type: 3-Wire Serial, Microwire, QSPI, SPI
• Operating Supply Voltage: 3 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TQFN-EP-32
• Maximum Power Dissipation: 2758 mW
• Minimum Operating Temperature: - 40 C
• Voltage Reference: 2.35 V to 3.6 V

Maxim Integrated
(4 CHANNEL)
1–10, 17, 19
MAX11335
MAX11338
20, 21
29–32
11
12
13
14
15
16
18
22
23
24
25
26
27
28
—
—
—
—
—
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
(8 CHANNEL)
5–10, 17, 19
MAX11336
MAX11339
29–32, 1–4
20, 21
11
12
13
14
15
16
18
22
23
24
25
26
27
28
—
—
—
—
—
(16 CHANNEL)
29–32 , 1–10
MAX11337
MAX11340
17, 19
20, 21
11
12
13
14
18
22
23
24
25
26
27
28
15
16
—
—
—
—
—
AIN0–AIN13 Analog Inputs
REF-/AIN15 External Differential Reference Negative Input /Analog Input 15
AIN0–AIN3
AIN0–AIN7
CNVST/
CNVST
NAME
DGND
OVDD
DOUT
AIN14
REF+
SCLK
GND
AON
REF-
EOC
AOP
V
AIN
DIN
AIP
CS
EP
DD
Ground
Positive Output from the Multiplexer
Negative Output from the Multiplexer
Positive Input to the ADC
Negative Input to the ADC
Active-Low Conversion Start Input
External Differential Reference Negative Input
External Positive Reference Input. Apply a reference voltage at
REF+. Bypass to GND with a 0.47FF capacitor.
Power-Supply Input. Bypass to GND with a 10FF in parallel with
a 0.1FF capacitors.
Serial Clock Input. Clocks data in and out of the serial interface.
Active-Low Chip Select Input. When CS is low, the serial
interface is enabled. When CS is high, DOUT is high
impedance or three-state.
Serial Data Input. DIN data is latched into the serial interface on
the rising edge of SCLK.
Digital I/O Ground
Digital Power-Supply Input. Bypass to GND with a 10FF in
parallel with a 0.1FF capacitors.
Serial Data Output. Data is clocked out on the falling edge of
SCLK. When CS is high, DOUT is high impedance or three-
state.
End of Conversion Output. Data is valid after EOC is driven low
(internal clock mode only).
Analog Inputs
Active-Low Conversion Start Input/Analog Input 14
Analog Inputs
Exposed Pad. Connect EP directly to GND plane for
guaranteed performance.
MAX11335–MAX11340
FUNCTION
Pin Description
12