MAX11339ATJ+ Maxim Integrated, MAX11339ATJ+ Datasheet - Page 25

• Manufacturer Part Number: MAX11339ATJ+
• Description: Analog to Digital Converters - ADC 10-Bit 8Ch 500ksps SAR ADC
• Manufacturer: Maxim Integrated

Specifications of MAX11339ATJ+

• Rohs: yes
• Number Of Channels: 8
• Architecture: SAR
• Conversion Rate: 500 kSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Differential
• Snr: 61.5 dB
• Interface Type: 3-Wire Serial, Microwire, QSPI, SPI
• Operating Supply Voltage: 3 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TQFN-EP-32
• Maximum Power Dissipation: 2758 mW
• Minimum Operating Temperature: - 40 C
• Voltage Reference: 2.35 V to 3.6 V

The MAX11335–MAX11340 communicate between the
internal registers and the external circuitry through the
SPI-/QSPI-compatible serial interface.
register access and control.
detail the various functions and configurations.
For ADC mode control, set bit 15 of the register code
identification to zero. The ADC Mode Control register
determines when and under what scan condition the
ADC operates.
To set the ADC data configuration, set the bit 15 of the
register code identification to one.
The MAX11335–MAX11340 feature three power-down
modes.
The devices shut down when the SPM bits in the ADC
Configuration register are asserted
two shutdown options:
Table 5. Power Management Modes
Table 6. ADC Configuration Register
Maxim Integrated
PM1
CONFIG_SETUP
0
0
1
1
BIT NAME
REFSEL
AVGON
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
PM0
Post-Mux External Signal Conditioning Access
0
1
0
1
Register Descriptions
AutoShutdown
AutoStandby
15:11
BIT
10
9
Normal
MODE
—
Table 2
DEFAULT
Power-Down Mode
STATE
N/A
(Table
0
0
Table 1
through
Static Shutdown
All circuitry is fully powered up at all times.
The device enters full shutdown mode at the end of each conversion. All circuitry
is powered down. The device powers up following the falling edge of CS. It takes 2
cycles before valid conversions take place. The information in the registers is retained.
The device powers down all circuitry except for the internal bias generator. The part
powers up following the falling edge of CS. It takes 2 cycles before valid conversions
take place. The information in the registers is retained.
Unused.
6). There are
Set to 10000 to select the ADC Configuration register.
Set to 1 to turn averaging on. Valid for internal clock mode only.
Set to 0 to turn averaging off.
REFSEL
details the
Table 14
0
1
VOLTAGE REFERENCE
External single-ended
External differential
U Full shutdown where all circuitry is shutdown.
U Partial shutdown where all circuitry is powered down
When the PM_ bits in the ADC Mode Control register are
asserted
edge of CS in the next frame. The device powers up
again at the following falling edge of CS. There are two
available options:
U AutoShutdown where all circuitry is shutdown.
U AutoStandby where all circuitry are powered down
The device shuts down after all conversions are complet-
ed. The device powers up again at the next falling edge
of CNVST or at the rising edge of CS after the SWCNV
bit is asserted.
except for the internal bias generator.
except for the internal bias generator.
MAX11335–MAX11340
(Table
FUNCTION
AutoShutdown with External Clock Mode
AutoShutdown with Internal Clock Mode
FUNCTION
5), the device shuts down at the rising
AIN15 (for the 16-channel devices)
REF- CONFIGURATION
REF-
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