MAX1302AEUG+ Maxim Integrated, MAX1302AEUG+ Datasheet - Page 18

• Manufacturer Part Number: MAX1302AEUG+
• Description: Analog to Digital Converters - ADC 16Bit, 8Ch, 4.096V Multi-In Serial ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1302AEUG+

• Rohs: yes
• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 115 kSPs
• Resolution: 16 bit
• Input Type: Single-Ended/Differential
• Snr: 90 dB
• Interface Type: SPI
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-24
• Maximum Power Dissipation: 1111.1 mW
• Number Of Converters: 1
• Voltage Reference: 4.096 V

The MAX1302 differential common-mode range
(V
valid conversion results. The differential common-mode
range is defined as:
In addition to the common-mode input voltage limita-
8-Channel, ±V
Serial 16-Bit ADC
Table 3. Input Data Word Formats
Table 4. Channel Selection in Single-Ended Mode (DIF/SGL = 0)
Table 5. Channel Selection in True-Differential Mode (DIF/SGL = 1)
18
Conversion-Start Byte
(Tables 4 and 5)
Analog-Input Configuration Byte
(Table 2)
Mode-Control Byte
(Table 7)
CMDR
C2
C2
CHANNEL-SELECT BIT
CHANNEL-SELECT BIT
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
______________________________________________________________________________________
) must remain within -4.75V to +5.5V to obtain
OPERATION
Differential Common-Mode Range
V
C1
C1
CMDR
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
=
C0
C0
(
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CH
_
+
)
2
CH0
CH0
+
+
+
REF
(
CH
(START)
D7
_
1
1
1
−
)
CH1
CH1
+
-
Multirange Inputs,
M2
D6
C2
C2
CH2
CH2
+
+
M1
D5
C1
C1
tions, each individual analog input must be limited to
±6V with respect to AGND1.
The range-select bits R[2:0] in the analog input config-
uration bytes determine the full-scale range for the cor-
responding channel (Tables 2 and 6). Figures 9, 10,
and 11 show the valid analog input voltage ranges for
the MAX1302 when operating with FSR = V
= V
area contains the valid common-mode voltage ranges
that support the entire FSR.
CH3
CH3
+
-
REF
, and FSR = 2 x V
RESERVED
RESERVED
RESERVED
RESERVED
CHANNEL
CHANNEL
M0
D4
C0
C0
DATA BIT
CH4
CH4
+
+
DIF/SGL
D3
0
1
CH5
CH5
+
-
REF
, respectively. The shaded
D2
R2
0
0
CH6
CH6
+
+
D1
R1
CH7
CH7
0
0
+
-
REF
AGND1
AGND1
/2, FSR
D0
R0
0
0
-
-
-
-
-
-
-
-