MAX1302AEUG+ Maxim Integrated, MAX1302AEUG+ Datasheet - Page 19

• Manufacturer Part Number: MAX1302AEUG+
• Description: Analog to Digital Converters - ADC 16Bit, 8Ch, 4.096V Multi-In Serial ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1302AEUG+

• Rohs: yes
• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 115 kSPs
• Resolution: 16 bit
• Input Type: Single-Ended/Differential
• Snr: 90 dB
• Interface Type: SPI
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-24
• Maximum Power Dissipation: 1111.1 mW
• Number Of Converters: 1
• Voltage Reference: 4.096 V

Figure 7. Single-Ended Input Voltage Ranges
The MAX1302 features a serial interface that is compat-
ible with SPI/QSPI and MICROWIRE devices. DIN,
DOUT, SCLK, CS, and SSTRB facilitate bidirectional
communication between the MAX1302 and the master
at SCLK rates up to 10MHz (internal clock mode,
mode 2), 3.67MHz (external clock mode, mode 0), or
4.39MHz (external acquisition mode, mode 1). The
master, typically a microcontroller, should use the
CPOL = 0, CPHA = 0, SPI transfer format, as shown in
the timing diagrams of Figures 2, 3, and 4.
The digital interface is used to:
• Select single-ended or true-differential input channel
• Select the unipolar or bipolar input range
• Select the mode of operation:
• Initiate conversions and read results
configurations
External clock (mode 0)
External acquisition (mode 1)
Internal clock (mode 2)
Reset (mode 4)
Partial power-down (mode 6)
Full power-down (mode 7)
+3
-3
+V
+V
-V
-V
/
/
4 V
4 V
+V
-V
REF
REF
REF
REF
REF
REF
REF
REF
/2
/4
/4
/2
0
EACH INPUT IS FAULT TOLERANT TO ±6V.
______________________________________________________________________________________
INPUT RANGE SELECTION BITS, R[2:0]
8-Channel, ±V
Digital Interface
CS enables communication with the MAX1302. When CS
is low, data is clocked into the device from DIN on the ris-
ing edge of SCLK and data is clocked out of DOUT on
the falling edge of SCLK. When CS is high, activity on
SCLK and DIN is ignored and DOUT is high impedance
allowing DOUT to be shared with other peripherals.
SSTRB is never high impedance and therefore cannot be
shared with other peripherals.
As shown in Figures 3 and 4, the SSTRB transitions high
to indicate that the ADC has completed a conversion
and results are ready to be read by the master. SSTRB
remains low in the external clock mode (Figure 2) and
consequently may be left unconnected. SSTRB is dri-
ven high or low regardless of the state of CS, therefore
SSTRB cannot be shared with other peripherals.
Figure 8. Differential Input Voltage Ranges
REF
+3
+2 x V
-3
-2 x V
+V
-V
/
/
2 V
2 V
+V
-V
REF
REF
REF
REF
REF
REF
REF
REF
/2
/2
0
Multirange Inputs,
EACH INPUT IS FAULT TOLERANT TO ±6V.
Serial 16-Bit ADC
INPUT RANGE SELECTION BITS, R[2:0]
Serial Strobe Output (SSTRB)
Chip Select (CS)
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