MAX1302AEUG+ Maxim Integrated, MAX1302AEUG+ Datasheet - Page 26

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MAX1302AEUG+

Manufacturer Part Number
MAX1302AEUG+
Description
Analog to Digital Converters - ADC 16Bit, 8Ch, 4.096V Multi-In Serial ADC
Manufacturer
Maxim Integrated
Datasheet

Specifications of MAX1302AEUG+

Rohs
yes
Number Of Channels
8/4
Architecture
SAR
Conversion Rate
115 kSPs
Resolution
16 bit
Input Type
Single-Ended/Differential
Snr
90 dB
Interface Type
SPI
Operating Supply Voltage
4.75 V to 5.25 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
TSSOP-24
Maximum Power Dissipation
1111.1 mW
Number Of Converters
1
Voltage Reference
4.096 V
The MAX1302 converts 1kHz signals more accurately
than a similar sigma-delta converter that might be con-
sidered in bridge applications. The input impedance of
the MAX1302, in combination with the current-limiting
resistors, can affect the gain of the MAX1302. In many
applications this error is acceptable, but for applica-
tions that cannot tolerate this error, the MAX1302 inputs
can be buffered (Figure 20). Connect the bridge to a
low-offset differential amplifier and then the true differ-
ential inputs of the MAX1302. Larger excitation voltages
take advantage of more of the ±V
voltage range. Select an input voltage range that
matches the amplifier output. Be aware of the amplifier
offset and offset-drift errors when selecting an appro-
priate amplifier.
Software control of each channel’s analog input range
and the unipolar endpoint overlap specification make it
possible for the user to change the input range for a
channel dynamically and improve performance in some
applications. Changing the input range results in a
small LSB step-size over a wider output voltage range.
For example, by switching between a -V
range and a 0V to V
but the input voltage range effectively spans from
-V
8-Channel, ±V
Serial 16-Bit ADC
Figure 18. External Reference Operation
26
REF
______________________________________________________________________________________
Dynamically Adjusting the Input Range
/2 to +V
REF
/2 (FSR = +V
(
REF
V
65 536 4 096
REF
,
MAX1302
/2 range, an LSB is:
ADC REF
SAR
2
)
×
REFERENCE
×
BANDGAP
REF
4.096V
V
.
REF
Bridge Application
5kΩ
).
REF
REF
4.096V
1x
/2 differential input
REF
Multirange Inputs,
/2 to 0V
V
REFCAP
RCTH
AGND1
REF
Careful PCB layout is essential for best system perfor-
mance. Boards should have separate analog and digital
ground planes and ensure that digital and analog sig-
nals are separated from each other. Do not run analog
and digital (especially clock) lines parallel to one anoth-
er, or digital lines underneath the device package.
Figure 1 shows the recommended system ground con-
nections. Establish an analog ground point at AGND1
and a digital ground point at DGND. Connect all analog
grounds to the star analog ground. Connect the digital
grounds to the star digital ground. Connect the digital
ground plane to the analog ground plane at one point.
For lowest noise operation, make the ground return to
the star ground’s power-supply low impedance and as
short as possible.
High-frequency noise in the AVDD1 power supply
degrades the ADC’s high-speed comparator perfor-
mance. Bypass AVDD1 to AGND1 with a 0.1µF ceramic
surface-mount capacitor. Make bypass capacitor con-
nections as short as possible.
INL is the deviation of the values on an actual transfer
function from a straight line. This straight line is either a
best straight-line fit or a line drawn between the end-
points of the transfer function once offset and gain
errors have been nullified. The MAX1302 INL is mea-
sured using the endpoint method.
AVDD1
1.0µF
Layout, Grounding, and Bypassing
OUT
MAX6341
GND
V+
IN
Parameter Definitions
Integral Nonlinearity (INL)
1.0µF

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