MAX1302AEUG+ Maxim Integrated, MAX1302AEUG+ Datasheet - Page 23

• Manufacturer Part Number: MAX1302AEUG+
• Description: Analog to Digital Converters - ADC 16Bit, 8Ch, 4.096V Multi-In Serial ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1302AEUG+

• Rohs: yes
• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 115 kSPs
• Resolution: 16 bit
• Input Type: Single-Ended/Differential
• Snr: 90 dB
• Interface Type: SPI
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-24
• Maximum Power Dissipation: 1111.1 mW
• Number Of Converters: 1
• Voltage Reference: 4.096 V

Figure 15. Analog Input Configuration Byte and Mode-Control Byte Timing
Figure 16. DOUT and SSTRB Timing
Table 7. Mode-Control Byte
BIT NUMBER
DOUT
SCLK
NOTE: SSTRB AND CS REMAIN LOW IN EXTERNAL CLOCK MODE (MODE 0).
DIN
CS
• User supplies one byte of SCLK, then drives CS
• After SSTRB transitions high, the user supplies
7
6
5
4
3
2
1
0
IMPEDANCE
high to relieve processor load while the ADC
converts
two bytes of SCLK and reads data at DOUT
t
t
DV
CSS
HIGH
t
DS
SSTRB
DOUT
SCLK
CS
START
t
SSCS
1
HIGH IMPEDANCE
BIT NAME
______________________________________________________________________________________
START
t
CL
M2
M1
M0
SEL2
1
0
0
0
t
CSS
ANALOG INPUT CONFIGURATION BYTE
SEL1
8-Channel, ±V
t
DO
Start Bit. The first logic 1 after CS goes low defines the beginning of the mode-control byte.
Mode-Control Bits. M[2:0] select the mode of operation as shown in Table 8.
Bit 3 must be a logic 1 for the mode-control byte.
Bit 2 must be a logic 0 for the mode-control byte.
Bit 1 must be a logic 0 for the mode-control byte.
Bit 0 must be a logic 0 for the mode-control byte.
SEL0
MSB
t
CP
DIF/SGL
t
CH
R2
R1
t
CSH
R0
t
t
8
DH
TR
IMPEDANCE
HIGH
The MAX1302’s fastest maximum throughput rate is
achieved operating in external clock mode. SCLK con-
trols both the acquisition and conversion of the analog
signal, facilitating precise control over when the analog
signal is captured. The analog input sampling instant is
at the falling edge of the 14th SCLK (Figure 2).
Since SCLK drives the conversion in external clock
mode, the SCLK frequency should remain constant
while the conversion is clocked. The minimum SCLK
frequency prevents droop in the internal sampling
capacitor voltages during conversion.
SSTRB remains low in the external clock mode, and as a
result may be left unconnected if the MAX1302 will
always be used in the external clock mode.
REF
t
CSPW
START
DESCRIPTION
1
M2
Multirange Inputs,
Serial 16-Bit ADC
M1
MODE CONTROL BYTE
M0
External Clock Mode (Mode 0)
1
0
0
0
8
IMPEDANCE
HIGH
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