CY7C1370D-200BGXC Cypress Semiconductor Corp, CY7C1370D-200BGXC Datasheet - Page 7

• Manufacturer Part Number: CY7C1370D-200BGXC
• Description: IC SRAM 18MBIT 200MHZ 119BGA
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1370D-200BGXC

• Memory Size: 18M (512K x 36)
• Package / Case: 119-BGA
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 3 ns
• Maximum Clock Frequency: 200 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 300 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Document Number: 38-05558 Rev. *H
Pin Definitions
A0
A1
A
BW
BW
BW
BW
WE
ADV/LD
CLK
CE
CE
CE
OE
CEN
DQ
DQP
MODE
TDO
TDI
TMS
TCK
Pin Name
1
2
3
S
a
b
c
d
X
asynchronous
Input strap pin Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
JTAG serial
JTAG serial
JTAG-clock
Input-clock
Test mode
I/O Type
output
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
select
input
I/O-
I/O-
Address inputs used to select one of the address locations. Sampled at the rising edge of
the CLK.
Byte write select inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BW
BW
Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
Advance/load input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD should
be driven LOW in order to load a new address.
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
Output enable, active LOW. Combined with the synchronous logic block inside the device to
control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked
during the data portion of a write sequence, during the first clock when emerging from a
deselected state and when the device has been deselected.
Clock enable input, active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A
controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave
as outputs. When HIGH, DQ
automatically three-stated during the data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is deselected, regardless of the state of
OE.
Bidirectional data parity I/O lines. Functionally, these signals are identical to DQ
sequences, DQP
and DQP
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK.
This pin controls the Test access port state machine. Sampled on the rising edge of TCK.
Clock input to the JTAG circuitry.
2
1
c
and CE
and CE
controls DQ
1
d
and CE
is controlled by BW
2
3
to select/deselect the device.
to select/deselect the device.
[17:0]
3
a
c
is controlled by BW
and DQP
to select/deselect the device.
during the previous clock rise of the read cycle. The direction of the pins is
c
a
, BW
–DQ
d
.
d
d
controls DQ
are placed in a three-state condition. The outputs are
a
, DQP
Pin Description
a
controls DQ
b
is controlled by BW
d
and DQP
a
and DQP
d
.
a
, BW
b
, DQP
b
CY7C1370DV25
CY7C1372DV25
controls DQ
c
is controlled by BW
s
. During write
b
and DQP
Page 7 of 29
b
c
,
,
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